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Re: [Qemu-arm] [PATCH 09/16] target-arm: Support multiple address spaces
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH 09/16] target-arm: Support multiple address spaces in page table walks |
Date: |
Mon, 9 Nov 2015 11:22:36 +0000 |
On 9 November 2015 at 11:19, Paolo Bonzini <address@hidden> wrote:
>
>
> On 09/11/2015 12:09, Peter Maydell wrote:
>>>> >> I could have handled that by making the CPU init code always
>>>> >> register two ASes (using the same one twice if the board code
>>>> >> only passes one or using system_address_space twice if the
>>>> >> board code doesn't pass one at all), but that seemed a bit wasteful.
>>> >
>>> > I think it's simpler though. Complicating the init code is better than
>>> > handling the condition throughout all the helpers...
>> It was the overhead of having an extra AddressSpace that concerned
>> me (plus it shows up in things like 'info mtree' somewhat confusingly
>> if you didn't expect your board to really have 2 ASes).
>
> I don't think it shows up twice with address_space_init_shareable, does it?
Yes, looking at the code you're right.
-- PMM
[Qemu-arm] [PATCH 11/16] memory: Add address_space_init_shareable(), Peter Maydell, 2015/11/05
[Qemu-arm] [PATCH 06/16] include/qom/cpu.h: Add new get_phys_page_asidx_debug method, Peter Maydell, 2015/11/05
[Qemu-arm] [PATCH 02/16] exec.c: Allow target CPUs to define multiple AddressSpaces, Peter Maydell, 2015/11/05