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Re: [Qemu-arm] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in a

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 1/8] target-arm: Properly support EL2 and EL3 in arm_el_is_aa64()
Date: Fri, 15 Jan 2016 14:50:24 +0000

On 15 January 2016 at 14:38, Edgar E. Iglesias <address@hidden> wrote:
> On Thu, Jan 14, 2016 at 06:34:04PM +0000, Peter Maydell wrote:
>> Support EL2 and EL3 in arm_el_is_aa64() by implementing the
>> logic for checking the SCR_EL3 and HCR_EL2 register-width bits
>> as appropriate to determine the register width of lower exception
>> levels.
>> Signed-off-by: Peter Maydell <address@hidden>
> Hi Peter,
> On the ZynqMP we've got the Cortex-A53 EL3 RW configurable at reset
> time. At some later point we'll likely have to implement that
> runtime option...

That might be tricky, we fairly well bake in "AARCH64 feature means
64-bit highest EL" at the moment. The KVM code takes the approach
of "if it's not going to reset in AArch64 then unset the feature bit".

Anyway, we'll cross that bridge when we get to it.

Do you have much locally extra that you needed for enabling
EL3 in the Cortex-A53? I have an ARM Trusted Firmware + OP-TEE
setup now that I'm going to use to work through the missing bits,
but if you've already gone through that effort there's no need
my duplicating work...

-- PMM

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