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[Qemu-arm] [PATCH 09/11] target-arm: In v8, make illegal AArch32 mode ch
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 09/11] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL |
Date: |
Mon, 15 Feb 2016 17:22:55 +0000 |
In v8, the illegal mode changes which are UNPREDICTABLE in v7 are
given architected behaviour:
* the mode field is unchanged
* PSTATE.IL is set (so any subsequent instructions will UNDEF)
* any other CPSR fields are written to as normal
This is pretty much the same behaviour we picked for our
UNPREDICTABLE handling, with the exception that for v8 we
need to set the IL bit.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e7b3eb3..69e93a2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5291,11 +5291,20 @@ void cpsr_write(CPUARMState *env, uint32_t val,
uint32_t mask,
(env->uncached_cpsr & CPSR_M) != CPSR_USER &&
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
if (bad_mode_switch(env, val & CPSR_M)) {
- /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
- * We choose to ignore the attempt and leave the CPSR M field
- * untouched.
+ /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
+ * v7, and has defined behaviour in v8:
+ * + leave CPSR.M untouched
+ * + allow changes to the other CPSR fields
+ * + set PSTATE.IL
+ * For user changes via the GDB stub, we don't set PSTATE.IL,
+ * as this would be unnecessarily harsh for a user error.
*/
mask &= ~CPSR_M;
+ if (write_type != CPSRWriteByGDBStub &&
+ arm_feature(env, ARM_FEATURE_V8)) {
+ mask |= CPSR_IL;
+ val |= CPSR_IL;
+ }
} else {
switch_mode(env, val & CPSR_M);
}
--
1.9.1
- [Qemu-arm] [PATCH 05/11] target-arm: In cpsr_write() ignore mode switches from User mode, (continued)
- [Qemu-arm] [PATCH 05/11] target-arm: In cpsr_write() ignore mode switches from User mode, Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 03/11] target-arm: Raw CPSR writes should skip checks and bank switching, Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 02/11] target-arm: Add write_type argument to cpsr_write(), Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 06/11] target-arm: Add comment about not implementing NSACR.RFR, Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 10/11] target-arm: Make mode switches from Hyp via CPS and MRS illegal, Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 09/11] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL,
Peter Maydell <=
- [Qemu-arm] [PATCH 11/11] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1, Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 07/11] target-arm: Add Hyp mode checks to bad_mode_switch(), Peter Maydell, 2016/02/15
- [Qemu-arm] [PATCH 01/11] target-arm: Give CPSR setting on 32-bit exception return its own helper, Peter Maydell, 2016/02/15