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Re: [Qemu-arm] [PATCH 4/4] target-arm: Avoid unnecessary TLB flush on TC
From: |
Sergey Fedorov |
Subject: |
Re: [Qemu-arm] [PATCH 4/4] target-arm: Avoid unnecessary TLB flush on TCR_EL2 writes |
Date: |
Mon, 4 Apr 2016 17:58:31 +0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 |
On 31/03/16 17:49, Peter Maydell wrote:
> The TCR_EL2 regdef was incorrectly using the vmsa_tcr_el1_write
> function for writes. Since TCR_EL2 doesn't have the A1 bit that
> TCR_EL1 does, we don't need to do a tlb_flush() when it is written.
> Remove the unnecessary .writefn and also the harmless but unneeded
> .raw_writefn and .resetfn definitions.
How about TCR_EL3 which doesn't have A1 bit as well?
Kind regards,
Sergey
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/helper.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 09638b2..4dbd844 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3559,8 +3559,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .resetvalue = 0 },
> { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
> - .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
> - .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> + .access = PL2_RW,
> + /* no .writefn needed as this can't cause an ASID change;
> + * no .raw_writefn or .resetfn needed as we never use mask/base_mask
> + */
> .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
> { .name = "VTCR", .state = ARM_CP_STATE_AA32,
> .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
- Re: [Qemu-arm] [PATCH 4/4] target-arm: Avoid unnecessary TLB flush on TCR_EL2 writes,
Sergey Fedorov <=