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Re: [Qemu-arm] [PATCH v5 13/14] aspeed: add a ram_size property to the m
From: |
Andrew Jeffery |
Subject: |
Re: [Qemu-arm] [PATCH v5 13/14] aspeed: add a ram_size property to the memory controller |
Date: |
Tue, 13 Sep 2016 12:25:58 +0930 |
On Fri, 2016-09-09 at 18:22 +0200, Cédric Le Goater wrote:
> Configure the size of the RAM of the SOC using a property to propagate
> the value down to the memory controller from the board level.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
> ---
> hw/arm/aspeed.c | 2 ++
> hw/arm/aspeed_soc.c | 2 ++
> hw/misc/aspeed_sdmc.c | 23 +++++++++++++----------
> include/hw/misc/aspeed_sdmc.h | 1 +
> 4 files changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 9013d35a674c..562bbb253391 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -113,6 +113,8 @@ static void aspeed_board_init(MachineState *machine,
> &bmc->ram);
> object_property_add_const_link(OBJECT(&bmc->soc), "ram",
> OBJECT(&bmc->ram),
> &error_abort);
> + object_property_set_int(OBJECT(&bmc->soc), ram_size, "ram-size",
> + &error_abort);
> object_property_set_int(OBJECT(&bmc->soc), cfg->hw_strap1, "hw-strap1",
> &error_abort);
> object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
> diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
> index 93bc7bb66e4b..c0a310205842 100644
> --- a/hw/arm/aspeed_soc.c
> +++ b/hw/arm/aspeed_soc.c
> @@ -113,6 +113,8 @@ static void aspeed_soc_init(Object *obj)
> qdev_set_parent_bus(DEVICE(&s->sdmc), sysbus_get_default());
> qdev_prop_set_uint32(DEVICE(&s->sdmc), "silicon-rev",
> sc->info->silicon_rev);
> + object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
> + "ram-size", &error_abort);
> }
>
> static void aspeed_soc_realize(DeviceState *dev, Error **errp)
> diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
> index 20bcdb52c4df..8830dc084c38 100644
> --- a/hw/misc/aspeed_sdmc.c
> +++ b/hw/misc/aspeed_sdmc.c
> @@ -140,9 +140,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
> .valid.max_access_size = 4,
> };
>
> -static int ast2400_rambits(void)
> +static int ast2400_rambits(AspeedSDMCState *s)
> {
> - switch (ram_size >> 20) {
> + switch (s->ram_size >> 20) {
> case 64:
> return ASPEED_SDMC_DRAM_64MB;
> case 128:
> @@ -156,14 +156,15 @@ static int ast2400_rambits(void)
> }
>
> /* use a common default */
> - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT
> - ". Using default 256M", ram_size);
> + error_report("warning: Invalid RAM size 0x%" PRIx64
> + ". Using default 256M", s->ram_size);
> + s->ram_size = 256 << 20;
> return ASPEED_SDMC_DRAM_256MB;
> }
>
> -static int ast2500_rambits(void)
> +static int ast2500_rambits(AspeedSDMCState *s)
> {
> - switch (ram_size >> 20) {
> + switch (s->ram_size >> 20) {
> case 128:
> return ASPEED_SDMC_AST2500_128MB;
> case 256:
> @@ -177,8 +178,9 @@ static int ast2500_rambits(void)
> }
>
> /* use a common default */
> - error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT
> - ". Using default 512M", ram_size);
> + error_report("warning: Invalid RAM size 0x%" PRIx64
> + ". Using default 512M", s->ram_size);
> + s->ram_size = 512 << 20;
> return ASPEED_SDMC_AST2500_512MB;
> }
>
> @@ -222,11 +224,11 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error
> **errp)
>
> switch (s->silicon_rev) {
> case AST2400_A0_SILICON_REV:
> - s->ram_bits = ast2400_rambits();
> + s->ram_bits = ast2400_rambits(s);
> break;
> case AST2500_A0_SILICON_REV:
> case AST2500_A1_SILICON_REV:
> - s->ram_bits = ast2500_rambits();
> + s->ram_bits = ast2500_rambits(s);
> break;
> default:
> g_assert_not_reached();
> @@ -249,6 +251,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
>
> static Property aspeed_sdmc_properties[] = {
> DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
> + DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h
> index df7dce0edddf..551c8afdf4be 100644
> --- a/include/hw/misc/aspeed_sdmc.h
> +++ b/include/hw/misc/aspeed_sdmc.h
> @@ -26,6 +26,7 @@ typedef struct AspeedSDMCState {
> uint32_t regs[ASPEED_SDMC_NR_REGS];
> uint32_t silicon_rev;
> uint32_t ram_bits;
> + uint64_t ram_size;
>
> } AspeedSDMCState;
>
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- [Qemu-arm] [PATCH v5 06/14] palmetto-bmc: add board specific configuration, (continued)
- [Qemu-arm] [PATCH v5 06/14] palmetto-bmc: add board specific configuration, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 07/14] hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 08/14] aspeed: add a ast2500 SoC and support to the SCU and SDMC controllers, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 09/14] arm: add support for an ast2500 evaluation board, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 10/14] palmetto-bmc: remove extra no_sdcard assignement, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 11/14] aspeed: calculate the RAM size bits at realize time, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 12/14] aspeed: use error_report instead of LOG_GUEST_ERROR, Cédric Le Goater, 2016/09/09
- [Qemu-arm] [PATCH v5 13/14] aspeed: add a ram_size property to the memory controller, Cédric Le Goater, 2016/09/09
- Re: [Qemu-arm] [PATCH v5 13/14] aspeed: add a ram_size property to the memory controller,
Andrew Jeffery <=
- [Qemu-arm] [PATCH v5 14/14] aspeed: allocate RAM after the memory controller has checked the size, Cédric Le Goater, 2016/09/09
- Re: [Qemu-arm] [PATCH v5 00/14] arm: add ast2500 support, Peter Maydell, 2016/09/19