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Re: [Qemu-arm] [PATCH 3/3] target/arm: Implement DBGVCR32_EL2 system reg
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-arm] [PATCH 3/3] target/arm: Implement DBGVCR32_EL2 system register |
Date: |
Thu, 12 Jan 2017 21:46:52 +0100 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Tue, Jan 10, 2017 at 06:44:09PM +0000, Peter Maydell wrote:
> The DBGVCR_EL2 system register is needed to run a 32-bit
> EL1 guest under a Linux EL2 64-bit hypervisor. Its only
> purpose is to provide AArch64 with access to the state of
> the DBGVCR AArch32 register. Since we only have a dummy
> DBGVCR, implement a corresponding dummy DBGVCR32_EL2.
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
> ---
> target/arm/helper.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index dc90986..bda562d 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4066,6 +4066,13 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
> .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
> .access = PL1_RW, .accessfn = access_tda,
> .type = ARM_CP_NOP },
> + /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor
> + * to save and restore a 32-bit guest's DBGVCR)
> + */
> + { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
> + .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
> + .access = PL2_RW, .accessfn = access_tda,
> + .type = ARM_CP_NOP },
> /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
> * Channel but Linux may try to access this register. The 32-bit
> * alias is DBGDCCINT.
> --
> 2.7.4
>
- [Qemu-arm] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2, Peter Maydell, 2017/01/10
- [Qemu-arm] [PATCH 3/3] target/arm: Implement DBGVCR32_EL2 system register, Peter Maydell, 2017/01/10
- Re: [Qemu-arm] [PATCH 3/3] target/arm: Implement DBGVCR32_EL2 system register,
Edgar E. Iglesias <=
- [Qemu-arm] [PATCH 2/3] target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32(), Peter Maydell, 2017/01/10
- [Qemu-arm] [PATCH 1/3] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts, Peter Maydell, 2017/01/10
- Re: [Qemu-arm] [PATCH 0/3] target/arm: Support EL1 AArch32 guest under AArch64 EL2, Edgar E. Iglesias, 2017/01/12