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[Qemu-arm] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff |
Date: |
Tue, 24 Jan 2017 19:16:20 +0000 |
For M profile (unlike A profile) the reset value of R14 is specified
as 0xffffffff. (The rationale is that this is an illegal exception
return value, so if guest code tries to return to it it will result
in a helpful exception.)
Registers r0 to r12 and the flags are architecturally UNKNOWN on
reset, so we leave those at zero.
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 0814f73..e9f10f7 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -196,6 +196,9 @@ static void arm_cpu_reset(CPUState *s)
*/
env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
+ /* Unlike A/R profile, M profile defines the reset LR value */
+ env->regs[14] = 0xffffffff;
+
/* Load the initial SP and PC from the vector table at address 0 */
rom = rom_ptr(0);
if (rom) {
--
2.7.4
- Re: [Qemu-arm] [PATCH 01/10] target/arm: Drop IS_M() macro, (continued)
- [Qemu-arm] [PATCH 07/10] armv7m: Report no-coprocessor faults correctly, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 09/10] armv7m: FAULTMASK should be 0 on reset, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 08/10] armv7m: Honour CCR.USERSETMPEND, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 05/10] armv7m: honour CCR.STACKALIGN on exception entry, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 10/10] armv7m: R14 should reset to 0xffffffff,
Peter Maydell <=
- [Qemu-arm] [PATCH 03/10] armv7m: add state for v7M CCR, CFSR, HFSR, DFSR, MMFAR, BFAR, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 04/10] armv7m: implement CCR, CFSR, HFSR, DFSR, BFAR, and MMFAR, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 02/10] armv7m_nvic: keep a pointer to the CPU, Peter Maydell, 2017/01/24
- [Qemu-arm] [PATCH 06/10] armv7m: set CFSR.UNDEFINSTR on undefined instructions, Peter Maydell, 2017/01/24