Re: [Qemu-arm] [PATCH v2 2/2] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts

[Edgar E. Iglesias]

On Mon, Feb 06, 2017 at 02:53:49PM +0000, Peter Maydell wrote:
> On 4 February 2017 at 14:31, Edgar E. Iglesias <address@hidden> wrote:
> > On Fri, Feb 03, 2017 at 05:48:55PM +0000, Peter Maydell wrote:
> >> Add support for generating the ISS (Instruction Specific Syndrome)
> >> for Data Abort exceptions taken from AArch32. These syndromes are
> >> used by hypervisors for example to trap and emulate memory accesses.
> >>
> >> This is the equivalent for AArch32 guests of the work done for AArch64
> >> guests in commit aaa1f954d4cab243.
> 
> >> +static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
> >> +{
> >> +    /* We don't need to save all of the syndrome so we mask and shift
> >> +     * out uneeded bits to help the sleb128 encoder do a better job.
> >> +     */
> >> +    syn &= ARM_INSN_START_WORD2_MASK;
> >> +    syn >>= ARM_INSN_START_WORD2_SHIFT;
> >> +
> >> +    /* We check and clear insn_start_idx to catch multiple updates.  */
> >> +    assert(s->insn_start_idx != 0);
> >> +    tcg_set_insn_param(s->insn_start_idx, 2, syn);
> >> +    s->insn_start_idx = 0;
> >> +}
> >
> > Could we move this into translate.h and share it with translate-a64.c?
> 
> Sure; I'll just squash that change into this patch and put the
> results into the target-arm queue, rather than burdening the
> list with a v3 respin, if that's OK.

Sounds good, thanks!

Cheers,
Edgar