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Re: [Qemu-arm] [PATCH V3 0/4] Add vPMU vPMU support under TCG mode
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH V3 0/4] Add vPMU vPMU support under TCG mode |
Date: |
Fri, 10 Feb 2017 15:00:13 +0000 |
On 7 February 2017 at 21:49, Wei Huang <address@hidden> wrote:
> QEMU has implemented cycle count support for guest VM under TCG mode.
> But this feature is not complete. In fact using perf inside a
> 64-bit Linux guest VM (under TCG) can cause the following kernel panic
> because some PMU registers are not implemented.
>
> [ 329.445970] [<fffffe000009e600>] armv8pmu_enable_event+0x58/0x8c
> [ 329.446713] [<fffffe0000621e74>] armpmu_start+0x4c/0x74
>
> This patchset solves the problem by adding support for missing vPMU
> registers. Basic perf test can work (both ACPI and DT) now under TCG
> by applying this patchset.
>
> address@hidden ~]# perf stat ls
> Performance counter stats for 'ls':
>
> 226.740256 task-clock (msec) # 0.312 CPUs utilized
> 76 context-switches # 0.335 K/sec
> 0 cpu-migrations # 0.000 K/sec
> 64 page-faults # 0.282 K/sec
> 186,031,410 cycles # 0.820 GHz (36.40%)
> <not supported> stalled-cycles-frontend
> <not supported> stalled-cycles-backend
> <not counted> instructions (0.00%)
> <not supported> branches
> <not counted> branch-misses (0.00%)
>
> V2->V3:
> * Remove PMXEVCNTR_EL0 support
> * Add read access support for PMXEVTYPER and change the CONSTRAINED
> UNPREDICTABLE behavior of PMXEVTYPER to RAZ/WI.
>
> V1->V2:
> * Change most PMU registers to 64bit and the behavior of PMXEVTYPER
> * Add support for PMXEVCNTR_EL0
> * Misc fixes (DT, ID_AA64DFR0_EL1, ...) under TCG mod
Applied to target-arm.next, thanks.
-- PMM