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Re: [Qemu-arm] [PATCH 3/9] armv7m: Rewrite NVIC to not use any GIC code

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 3/9] armv7m: Rewrite NVIC to not use any GIC code
Date: Sat, 18 Feb 2017 18:38:49 +0000

On 18 February 2017 at 17:45, Michael Davidsaver <address@hidden> wrote:
> On 02/16/2017 09:11 AM, Peter Maydell wrote:
>> I haven't actually checked real hardware behaviour, but I think
>> we can fairly safely implement this as not checking the IPSR
>> exception field. (We might as well go with the "reads 1 in
>> handler mode" choice of UNKNOWN that the M3 documents, though.)
> For what it's worth, I dug up my TI TM4C1294 eval board and re-ran
> test10.c [1] which is designed to probe this behavior by nesting
> exceptions PendSV within SVC.  RETTOBASE is 0x800 in ICSR.

That's a Cortex-M4. From the test it looks like it
has a different choice of UNKNOWN behaviour for
the value in Handler mode, so real code in the field
isn't going to be relying on that and it doesn't
matter what we choose.

I don't think the test looks at the "what happens if the
exception in the IPSR exception field isn't actually
active" case, right?

-- PMM

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