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[Qemu-arm] [PATCH] target/aarch64: exit to main loop after 'msr daifclr'


From: Emilio G. Cota
Subject: [Qemu-arm] [PATCH] target/aarch64: exit to main loop after 'msr daifclr'
Date: Wed, 14 Jun 2017 16:33:43 -0400
User-agent: Mutt/1.5.24 (2015-08-30)

On Wed, Jun 14, 2017 at 12:48:21 -0700, Richard Henderson wrote:
> Exit to cpu loop so we reevaluate cpu_arm_hw_interrupts.
> 
> Cc: address@hidden
> Cc: Peter Maydell <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate-a64.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 860e279..e55547d 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -1422,7 +1422,9 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
>          gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
>          tcg_temp_free_i32(tcg_imm);
>          tcg_temp_free_i32(tcg_op);
> -        s->is_jmp = DISAS_UPDATE;
> +        /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs.  */
> +        gen_a64_set_pc_im(s->pc);

For op != 0x1f we end up setting the pc twice (first here, then in
the switch statement). It's still correct though.

> +        s->is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP);

Could do without the parens.

>          break;
>      }
>      default:
> @@ -11369,6 +11371,9 @@ void gen_intermediate_code_a64(ARMCPU *cpu, 
> TranslationBlock *tb)
>          case DISAS_JUMP:
>              tcg_gen_lookup_and_goto_ptr(cpu_pc);
>              break;
> +        case DISAS_EXIT:
> +            tcg_gen_exit_tb(0);
> +            break;

We could also mention the regression in the commit log. In fact
I just did that :-) feel free to reuse parts of the below.

Thanks,

                E.

--- 8< ---

Commit e75449a3 ("target/aarch64: optimize indirect branches") causes
a regression by which -smp > 1 freezes under TCG, even with
`-accel accel=tcg,thread=single' (i.e. MTTCG disabled).

The cause of the regression is well described here by Alex:
On Wed, Jun 14, 2017 at 15:02:06 +0100, Alex Bennée wrote:
> Fundamentally the problem was that an interrupt was pending
> (interrupt_request was set) but the "msr daifclr" operations when the
> kernel did local_irq/fiq_enable() never got handled because the
> cpu_idle loop was being very efficiently chained. As a result we never
> got around to exiting the TCG code and calling arm_cpu_do_interrupt
> which would then raise the IRQ to move things on
> [ Message-Id: <address@hidden> ]

Fix it by enforcing an exit to the main loop right after 'msr daifclr'
is executed.

Signed-off-by: Emilio G. Cota <address@hidden>
---
 target/arm/translate-a64.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 860e279..323e419 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1422,7 +1422,8 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
         gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
         tcg_temp_free_i32(tcg_imm);
         tcg_temp_free_i32(tcg_op);
-        s->is_jmp = DISAS_UPDATE;
+        /* force exit to the main loop for DAIFClear */
+        s->is_jmp = op == 0x1f ? DISAS_EXIT : DISAS_UPDATE;
         break;
     }
     default:
@@ -11362,6 +11363,10 @@ void gen_intermediate_code_a64(ARMCPU *cpu, 
TranslationBlock *tb)
         case DISAS_NEXT:
             gen_goto_tb(dc, 1, dc->pc);
             break;
+        case DISAS_EXIT:
+            gen_a64_set_pc_im(dc->pc);
+            tcg_gen_exit_tb(0);
+            break;
         default:
         case DISAS_UPDATE:
             gen_a64_set_pc_im(dc->pc);
-- 
2.7.4




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