Re: [Qemu-arm] [PATCH 2/8] target/arm: Use generic vector infrastructure for aa64 add/sub/logic

[Richard Henderson]

On 09/07/2017 09:58 AM, Alex Bennée wrote:
>> +    switch (size + 4 * is_u) {
> 
> Hmm I find this switch a little too magical. I mean I can see that the
> encoding abuses size for the final opcode when I look at the manual but
> it reads badly.
> 
>> +    case 0: /* AND */
>> +        gvec_op = tcg_gen_gvec_and8;
>> +        goto do_gvec;
>> +    case 1: /* BIC */
>> +        gvec_op = tcg_gen_gvec_andc8;
>> +        goto do_gvec;
>> +    case 2: /* ORR */
>> +        gvec_op = tcg_gen_gvec_or8;
>> +        goto do_gvec;
>> +    case 3: /* ORN */
>> +        gvec_op = tcg_gen_gvec_orc8;
>> +        goto do_gvec;
>> +    case 4: /* EOR */
>> +        gvec_op = tcg_gen_gvec_xor8;
>> +        goto do_gvec;
>> +    do_gvec:
>> +        gvec_op(vec_full_reg_offset(s, rd),
>> +                vec_full_reg_offset(s, rn),
>> +                vec_full_reg_offset(s, rm),
>> +                is_q ? 16 : 8, vec_full_reg_size(s));
>> +        return;
> 
> No default case (although I guess we just fall through). What's wrong
> with just having a !is_u test with gvec_op = tbl[size] and skipping all
> the goto stuff?

Because that would still leave EOR out in the woods.
I do think this is the cleanest way to filter out these 5 operations.


r~