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Re: [Qemu-arm] [PATCH v2] arm: implement cache/shareability attribute bi


From: Andrew Baumann
Subject: Re: [Qemu-arm] [PATCH v2] arm: implement cache/shareability attribute bits for PAR registers
Date: Tue, 31 Oct 2017 10:28:33 +0000

> From: Peter Maydell [mailto:address@hidden
> Sent: Tuesday, 31 October 2017 17:53
> 
> On 31 October 2017 at 01:23, Andrew Baumann
> <address@hidden> wrote:
> >> From: Peter Maydell [mailto:address@hidden
> >> Hi. This is looking pretty good, but I have a few comments below,
> >> and we're pretty much at the softfreeze date (KVM Forum last week
> >> meant I didn't get much code review done, unfortunately). Would
> >> you be too sad if this missed 2.11 ?
> >
> > No worries. It would be nice to have a stable release that we can tell 
> > people
> supports arm64 Windows, but I recognise that this is a non-trivial change, so 
> if
> we have to wait for 2.12 to get that, then fair enough.
> 
> Is this the only missing piece, then? If we squint a bit we can
> call it a bug fix as long as we can get it in early in the softfreeze
> rather than later...

It is the last piece, and I'll try to get you a v3 soon, but this week it's my 
turn to be travelling, so it may take a day or two. I'll understand if we don't 
get it in -- not a show-stopper.

> >> The v8A ARM ARM pseudocode CombineS1S2AttrHints() says that the hint
> >> bits always come from s1 regardless of whose attrs won.
> >
> > Aha, I was wondering about this. Thanks for the pointer to the pseudocode...
> it isn't referenced anywhere in the relevant section! It's reassuring to see 
> that,
> aside from the hints (where the English was ambiguous IIRC), I seem to have
> got the rest of the translation correct.
> 
> I didn't find anything in the English text about hints at all.
> (I'll have to go and have another look.)

I didn't find any mention of it. That's pretty ambiguous IMO :)

Andrew

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