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Re: [Qemu-arm] [PATCH 12/13] sdhci: Add i.MX specific subtype of SDHCI

From: Philippe Mathieu-Daudé
Subject: Re: [Qemu-arm] [PATCH 12/13] sdhci: Add i.MX specific subtype of SDHCI
Date: Thu, 14 Dec 2017 12:32:30 -0300
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0

Hi Andrey,

On 12/14/2017 11:03 AM, Andrey Smirnov wrote:
> On Tue, Dec 12, 2017 at 9:52 AM, Peter Maydell <address@hidden> wrote:
>> On 11 December 2017 at 21:30, Andrey Smirnov <address@hidden> wrote:
>>> +    case ESDHC_DLL_CTRL:
>>> +    case 0x6c:
>> Isn't there a name we can give 0x6c ?
> Unfortunately, not that I know of. It's a mystery register not listed
> in RM and the only place I can found it being mentioned is in Linux
> driver as a part of errata ESDHC_FLAG_ERR004536 fix, where it is used
> nameless as well.

This sets the SD CLK/RCLK frequency (10-bit) for the 104MB/sec bus speed
(UHS-I mode).

The "Sampling Clock Tuning Procedure" figure in the Spec v3 is helpful.

In my tree (where I work on UHS-I/II) I have:

#define SDHC_PRESET_SDR104              0x6c
FIELD(SDHC_PRESET_SDR104, CLKFREQ,           0, 10); /* since v3 */
FIELD(SDHC_PRESET_SDR104, CLKGEN,           10,  1); /* since v3 */
FIELD(SDHC_PRESET_SDR104, DRIVE_STRENGTH,   14,  2); /* since v3 (UHS-I
only) */



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