Re: [Qemu-arm] [Qemu-devel] [PATCH 4/8] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only

[Alistair Francis]

On Wed, Dec 13, 2017 at 6:00 PM, Philippe Mathieu-Daudé <address@hidden> wrote:
> running qtests:
>
>   $ make check-qtest-arm
>     GTESTER check-qtest-arm
>   SDHC rd_4b @0x44 not implemented
>   SDHC wr_4b @0x40 <- 0x89abcdef not implemented
>   SDHC wr_4b @0x44 <- 0x01234567 not implemented
>
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>  include/hw/sd/sdhci.h |  4 ++--
>  hw/sd/sdhci.c         | 25 ++++++++++++++++++++-----
>  2 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index f8e91ce903..d5093fe3fd 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -75,8 +75,8 @@ typedef struct SDHCIState {
>      uint16_t acmd12errsts; /* Auto CMD12 error status register */
>      uint64_t admasysaddr;  /* ADMA System Address Register */
>
> -    uint32_t capareg;      /* Capabilities Register */
> -    uint32_t maxcurr;      /* Maximum Current Capabilities Register */
> +    uint64_t capareg;      /* Capabilities Register */
> +    uint64_t maxcurr;      /* Maximum Current Capabilities Register */
>      uint8_t  *fifo_buffer; /* SD host i/o FIFO buffer */
>      uint32_t buf_maxsz;
>      uint16_t data_count;   /* current element in FIFO buffer */
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index d6145342fb..4d269c7ac4 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -99,7 +99,7 @@
>
>  static void sdhci_init_capareg(SDHCIState *s, Error **errp)
>  {
> -    if (s->capareg == UINT32_MAX) {
> +    if (s->capareg == UINT64_MAX) {
>          s->capareg = SDHC_CAPAB_REG_DEFAULT;
>      }
>  }
> @@ -893,10 +893,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, 
> unsigned size)
>          ret = s->acmd12errsts;
>          break;
>      case SDHC_CAPAREG:
> -        ret = s->capareg;
> +        ret = (uint32_t)s->capareg;
> +        break;
> +    case SDHC_CAPAREG + 4:
> +        ret = (uint32_t)(s->capareg >> 32);
>          break;
>      case SDHC_MAXCURR:
> -        ret = s->maxcurr;
> +        ret = (uint32_t)s->maxcurr;
> +        break;
> +    case SDHC_MAXCURR + 4:
> +        ret = (uint32_t)(s->maxcurr >> 32);
>          break;
>      case SDHC_ADMAERR:
>          ret =  s->admaerr;
> @@ -1117,6 +1123,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, 
> unsigned size)
>          }
>          sdhci_update_irq(s);
>          break;
> +
> +    case SDHC_CAPAREG:
> +    case SDHC_CAPAREG + 4:
> +    case SDHC_MAXCURR:
> +    case SDHC_MAXCURR + 4:
> +        qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
> +                      " <- 0x%08x read-only\n", size, offset, value >> 
> shift);
> +        break;
> +
>      default:
>          qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 
> 0x%08x "
>                        "not implemented\n", size, offset, value >> shift);
> @@ -1266,8 +1281,8 @@ const VMStateDescription sdhci_vmstate = {
>  static Property sdhci_properties[] = {
>      DEFINE_PROP_UINT8("sd-spec-version", SDHCIState,
>                        capabilities.spec_version, SD_HOST_SPECv2_VERS),
> -    DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, UINT32_MAX),
> -    DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0),
> +    DEFINE_PROP_UINT64("capareg", SDHCIState, capareg, UINT64_MAX),
> +    DEFINE_PROP_UINT64("maxcurr", SDHCIState, maxcurr, 0),
>      DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, 
> pending_insert_quirk,
>                       false),
>      DEFINE_PROP_LINK("dma-memory", SDHCIState, dma_mr,
> --
> 2.15.1
>
>