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Re: [Qemu-arm] [PATCH 0/4] arm_gic: Various fixes

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH 0/4] arm_gic: Various fixes
Date: Mon, 22 Jan 2018 15:36:01 +0000

On 19 January 2018 at 14:57,  <address@hidden> wrote:
> Here is a patch set for issues I found in the GIC. I found those by
> writing unitary tests for the GIC, and compared the result against
> real hardware (a Zynq UltraScale+ board with a GICv2).
> The first patch prevents the GIC from signaling an IRQ that is in the
> "active and pending" state. I encountered this bug in a test where I
> split end of interrupt and interrupt deactivation. The GIC was
> re-signaling the IRQ after priority drop if it was raised again, while
> it has not been deactivated yet (and thus was in the "active and
> pending" state).
> The second patch returns a correct "Idle priority" value when reading
> C_RPR if there is no active interrupt.
> The last two patches fix issues around the Binary Point Register (the
> group priority computation of group 1 IRQs when C_CTRL.CBPR is 0, and
> the non-secure view of C_BPR when C_CTRL.CBPR is 1).

Thanks for this patchset, and in particular for the detailed
commit messages that made it really easy to review.
Since there were only a couple of minor nits in the patchset
(an extra assert, a comment typo) I'm going to take this into
target-arm.next and fix those things there, rather than ask you
to respin the patchset.

-- PMM

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