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[Qemu-arm] [PATCH v3-a 03/27] target/arm: Implement SVE Bitwise Logical
From: |
Richard Henderson |
Subject: |
[Qemu-arm] [PATCH v3-a 03/27] target/arm: Implement SVE Bitwise Logical - Unpredicated Group |
Date: |
Wed, 16 May 2018 15:29:43 -0700 |
These were the instructions that were stubbed out when
introducing the decode skeleton.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
v3: Remove typedefs now present in translate-a64.h.
---
target/arm/translate-sve.c | 55 ++++++++++++++++++++++++++++++++------
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index d323bd0b67..67d6db313e 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -42,22 +42,61 @@
* Implement all of the translator functions referenced by the decoder.
*/
-static bool trans_AND_zzz(DisasContext *s, arg_AND_zzz *a, uint32_t insn)
+/* Invoke a vector expander on two Zregs. */
+static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
+ int esz, int rd, int rn)
{
- return false;
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), vsz, vsz);
+ }
+ return true;
}
-static bool trans_ORR_zzz(DisasContext *s, arg_ORR_zzz *a, uint32_t insn)
+/* Invoke a vector expander on three Zregs. */
+static bool do_vector3_z(DisasContext *s, GVecGen3Fn *gvec_fn,
+ int esz, int rd, int rn, int rm)
{
- return false;
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm), vsz, vsz);
+ }
+ return true;
}
-static bool trans_EOR_zzz(DisasContext *s, arg_EOR_zzz *a, uint32_t insn)
+/* Invoke a vector move on two Zregs. */
+static bool do_mov_z(DisasContext *s, int rd, int rn)
{
- return false;
+ return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
}
-static bool trans_BIC_zzz(DisasContext *s, arg_BIC_zzz *a, uint32_t insn)
+/*
+ *** SVE Logical - Unpredicated Group
+ */
+
+static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
{
- return false;
+ return do_vector3_z(s, tcg_gen_gvec_and, 0, a->rd, a->rn, a->rm);
+}
+
+static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ if (a->rn == a->rm) { /* MOV */
+ return do_mov_z(s, a->rd, a->rn);
+ } else {
+ return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
+ }
+}
+
+static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_xor, 0, a->rd, a->rn, a->rm);
+}
+
+static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
}
--
2.17.0
- [Qemu-arm] [PATCH v3-a 00/27] target/arm: Scalable Vector Extension, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 01/27] target/arm: Introduce translate-a64.h, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 02/27] target/arm: Add SVE decode skeleton, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 03/27] target/arm: Implement SVE Bitwise Logical - Unpredicated Group,
Richard Henderson <=
- [Qemu-arm] [PATCH v3-a 04/27] target/arm: Implement SVE load vector/predicate, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 05/27] target/arm: Implement SVE predicate test, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 06/27] target/arm: Implement SVE Predicate Logical Operations Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 07/27] target/arm: Implement SVE Predicate Misc Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 09/27] target/arm: Implement SVE Integer Reduction Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 08/27] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Richard Henderson, 2018/05/16
- [Qemu-arm] [PATCH v3-a 12/27] target/arm: Implement SVE bitwise shift by wide elements (predicated), Richard Henderson, 2018/05/16