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Re: [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET |
Date: |
Thu, 28 Jun 2018 17:23:47 +0100 |
On 22 June 2018 at 21:32, Aaron Lindsay <address@hidden> wrote:
> Add an array for PMOVSSET so we only define it for v7ve+ platforms
>
> Signed-off-by: Aaron Lindsay <address@hidden>
> ---
> target/arm/helper.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 7d63bb2..5d83446 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -1293,9 +1293,17 @@ static void pmcntenclr_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + value &= pmu_counter_mask(env);
> env->cp15.c9_pmovsr &= ~value;
> }
This change doesn't look like it should be in this patch ?
>
> +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + value &= pmu_counter_mask(env);
> + env->cp15.c9_pmovsr |= value;
> +}
> +
> static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -1645,6 +1653,23 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
> REGINFO_SENTINEL
> };
>
> +static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
> + /* PMOVSSET is not implemented in v7 before v7ve */
> + { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 =
> 3,
> + .access = PL0_RW, .accessfn = pmreg_access,
> + .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
> + .writefn = pmovsset_write,
> + .raw_writefn = raw_write },
This should be marked ARM_CP_ALIAS, beacuse its underlying
state in c9_pmovsr is just an alias into PMOVSR, and that
register is handling reset and migration.
> + { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
> + .access = PL0_RW, .accessfn = pmreg_access,
> + .type = ARM_CP_ALIAS,
> + .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
> + .writefn = pmovsset_write,
> + .raw_writefn = raw_write },
> + REGINFO_SENTINEL
> +};
> +
> static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> @@ -4996,6 +5021,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> !arm_feature(env, ARM_FEATURE_PMSA)) {
> define_arm_cp_regs(cpu, v7mp_cp_reginfo);
> }
> + if (arm_feature(env, ARM_FEATURE_V7VE)) {
> + define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
> + }
> if (arm_feature(env, ARM_FEATURE_V7)) {
> /* v7 performance monitor control register: same implementor
> * field as main ID register, and we implement only the cycle
> --
thanks
-- PMM
- [Qemu-arm] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses, (continued)
- [Qemu-arm] [PATCH v5 01/13] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 03/13] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 02/13] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 04/13] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 05/13] target/arm: Remove redundant DIV detection for KVM, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/06/22
- Re: [Qemu-arm] [PATCH v5 06/13] target/arm: Implement PMOVSSET,
Peter Maydell <=
- [Qemu-arm] [PATCH v5 07/13] target/arm: Add array for supported PMU events, generate PMCEID[01], Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 08/13] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 09/13] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 10/13] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 11/13] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 13/13] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/06/22
- [Qemu-arm] [PATCH v5 12/13] target/arm: Mark PMINTENSET accesses as possibly doing IO, Aaron Lindsay, 2018/06/22
- Re: [Qemu-arm] [PATCH v5 00/13] More fully implement ARM PMUv3, Peter Maydell, 2018/06/28