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Re: [Qemu-arm] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn
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From: |
Emilio G. Cota |
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Subject: |
Re: [Qemu-arm] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM |
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Date: |
Fri, 13 Jul 2018 12:41:21 -0400 |
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User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Tue, Jul 10, 2018 at 17:00:11 +0100, Peter Maydell wrote:
> If get_page_addr_code() returns -1, this indicates that there is no RAM
> page we can read a full TB from. Instead we must create a TB which
> contains a single instruction and which we do not cache, so it is
> executed only once.
>
> Since this means we can now have TBs which are not in any page list,
> we also need to make tb_phys_invalidate() handle them (by not trying
> to remove them from a nonexistent page list).
>
> Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Emilio
- [Qemu-arm] [PATCH 0/6] accel/tcg: Support execution from MMIO and small MMU regions, Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 2/6] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups, Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 1/6] accel/tcg: Pass read access type through to io_readx(), Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM, Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 3/6] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint(), Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 6/6] target/arm: Allow execution from small regions, Peter Maydell, 2018/07/10
- [Qemu-arm] [PATCH 5/6] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code(), Peter Maydell, 2018/07/10
- Re: [Qemu-arm] [PATCH 0/6] accel/tcg: Support execution from MMIO and small MMU regions, Philippe Mathieu-Daudé, 2018/07/11