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Re: [Qemu-arm] [Qemu-devel] [PATCH v1 03/12] net: cadence_gem: Use uint3
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-arm] [Qemu-devel] [PATCH v1 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words |
Date: |
Sat, 6 Oct 2018 01:09:55 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 03/10/2018 17:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Use uint32_t instead of unsigned to describe 32bit descriptor words.
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> hw/net/cadence_gem.c | 42 +++++++++++++++++++++---------------------
> include/hw/net/cadence_gem.h | 2 +-
> 2 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
> index 901c173..31f3fe0 100644
> --- a/hw/net/cadence_gem.c
> +++ b/hw/net/cadence_gem.c
> @@ -302,42 +302,42 @@
>
> #define GEM_MODID_VALUE 0x00020118
>
> -static inline unsigned tx_desc_get_buffer(unsigned *desc)
> +static inline unsigned tx_desc_get_buffer(uint32_t *desc)
> {
> return desc[0];
> }
>
> -static inline unsigned tx_desc_get_used(unsigned *desc)
> +static inline unsigned tx_desc_get_used(uint32_t *desc)
> {
> return (desc[1] & DESC_1_USED) ? 1 : 0;
> }
>
> -static inline void tx_desc_set_used(unsigned *desc)
> +static inline void tx_desc_set_used(uint32_t *desc)
> {
> desc[1] |= DESC_1_USED;
> }
>
> -static inline unsigned tx_desc_get_wrap(unsigned *desc)
> +static inline unsigned tx_desc_get_wrap(uint32_t *desc)
> {
> return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
> }
>
> -static inline unsigned tx_desc_get_last(unsigned *desc)
> +static inline unsigned tx_desc_get_last(uint32_t *desc)
> {
> return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
> }
>
> -static inline void tx_desc_set_last(unsigned *desc)
> +static inline void tx_desc_set_last(uint32_t *desc)
> {
> desc[1] |= DESC_1_TX_LAST;
> }
>
> -static inline unsigned tx_desc_get_length(unsigned *desc)
> +static inline unsigned tx_desc_get_length(uint32_t *desc)
> {
> return desc[1] & DESC_1_LENGTH;
> }
>
> -static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
> +static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
> {
> DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
> DB_PRINT("bufaddr: 0x%08x\n", *desc);
> @@ -347,58 +347,58 @@ static inline void print_gem_tx_desc(unsigned *desc,
> uint8_t queue)
> DB_PRINT("length: %d\n", tx_desc_get_length(desc));
> }
>
> -static inline unsigned rx_desc_get_buffer(unsigned *desc)
> +static inline unsigned rx_desc_get_buffer(uint32_t *desc)
> {
> return desc[0] & ~0x3UL;
> }
>
> -static inline unsigned rx_desc_get_wrap(unsigned *desc)
> +static inline unsigned rx_desc_get_wrap(uint32_t *desc)
> {
> return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
> }
>
> -static inline unsigned rx_desc_get_ownership(unsigned *desc)
> +static inline unsigned rx_desc_get_ownership(uint32_t *desc)
> {
> return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
> }
>
> -static inline void rx_desc_set_ownership(unsigned *desc)
> +static inline void rx_desc_set_ownership(uint32_t *desc)
> {
> desc[0] |= DESC_0_RX_OWNERSHIP;
> }
>
> -static inline void rx_desc_set_sof(unsigned *desc)
> +static inline void rx_desc_set_sof(uint32_t *desc)
> {
> desc[1] |= DESC_1_RX_SOF;
> }
>
> -static inline void rx_desc_set_eof(unsigned *desc)
> +static inline void rx_desc_set_eof(uint32_t *desc)
> {
> desc[1] |= DESC_1_RX_EOF;
> }
>
> -static inline void rx_desc_set_length(unsigned *desc, unsigned len)
> +static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
> {
> desc[1] &= ~DESC_1_LENGTH;
> desc[1] |= len;
> }
>
> -static inline void rx_desc_set_broadcast(unsigned *desc)
> +static inline void rx_desc_set_broadcast(uint32_t *desc)
> {
> desc[1] |= R_DESC_1_RX_BROADCAST;
> }
>
> -static inline void rx_desc_set_unicast_hash(unsigned *desc)
> +static inline void rx_desc_set_unicast_hash(uint32_t *desc)
> {
> desc[1] |= R_DESC_1_RX_UNICAST_HASH;
> }
>
> -static inline void rx_desc_set_multicast_hash(unsigned *desc)
> +static inline void rx_desc_set_multicast_hash(uint32_t *desc)
> {
> desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
> }
>
> -static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
> +static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
> {
> desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT,
> R_DESC_1_RX_SAR_LENGTH,
> sar_idx);
> @@ -1042,7 +1042,7 @@ static void gem_transmit_updatestats(CadenceGEMState
> *s, const uint8_t *packet,
> */
> static void gem_transmit(CadenceGEMState *s)
> {
> - unsigned desc[2];
> + uint32_t desc[2];
> hwaddr packet_desc_addr;
> uint8_t tx_packet[2048];
> uint8_t *p;
> @@ -1108,7 +1108,7 @@ static void gem_transmit(CadenceGEMState *s)
>
> /* Last descriptor for this packet; hand the whole thing off */
> if (tx_desc_get_last(desc)) {
> - unsigned desc_first[2];
> + uint32_t desc_first[2];
>
> /* Modify the 1st descriptor of this packet to be owned by
> * the processor.
> diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
> index 35de622..633d564 100644
> --- a/include/hw/net/cadence_gem.h
> +++ b/include/hw/net/cadence_gem.h
> @@ -74,7 +74,7 @@ typedef struct CadenceGEMState {
>
> uint8_t can_rx_state; /* Debug only */
>
> - unsigned rx_desc[MAX_PRIORITY_QUEUES][2];
> + uint32_t rx_desc[MAX_PRIORITY_QUEUES][2];
>
> bool sar_active[4];
> } CadenceGEMState;
>
- [Qemu-arm] [PATCH v1 00/12] arm: Add first models of Xilinx Versal SoC, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 01/12] net: cadence_gem: Disable TSU feature bit, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 02/12] net: cadence_gem: Announce availability of priority queues, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 03/12] net: cadence_gem: Use uint32_t for 32bit descriptor words, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 04/12] net: cadence_gem: Add macro with max number of descriptor words, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 05/12] net: cadence_gem: Add support for extended descriptors, Edgar E. Iglesias, 2018/10/03
- [Qemu-arm] [PATCH v1 06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion, Edgar E. Iglesias, 2018/10/03