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[Qemu-arm] [PATCH v6 02/14] target/arm: Mask PMOVSR writes based on supp
From: |
Aaron Lindsay |
Subject: |
[Qemu-arm] [PATCH v6 02/14] target/arm: Mask PMOVSR writes based on supported counters |
Date: |
Wed, 10 Oct 2018 16:37:23 -0400 |
This is an amendment to my earlier patch:
commit 7ece99b17e832065236c07a158dfac62619ef99b
Author: Aaron Lindsay <address@hidden>
Date: Thu Apr 26 11:04:39 2018 +0100
target/arm: Mask PMU register writes based on PMCR_EL0.N
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 52c76b7444..8ca4d30797 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1179,6 +1179,7 @@ static void pmcntenclr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ value &= pmu_counter_mask(env);
env->cp15.c9_pmovsr &= ~value;
}
--
2.19.1
- [Qemu-arm] [PATCH v6 00/14] More fully implement ARM PMUv3, Aaron Lindsay, 2018/10/10
- [Qemu-arm] [PATCH v6 07/14] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/10/10
- [Qemu-arm] [PATCH v6 01/14] target/arm: Mark PMINTENCLR and PMINTENCLR_EL1 accesses as possibly doing IO, Aaron Lindsay, 2018/10/10
- [Qemu-arm] [PATCH v6 02/14] target/arm: Mask PMOVSR writes based on supported counters,
Aaron Lindsay <=
- [Qemu-arm] [PATCH v6 04/14] target/arm: Swap PMU values before/after migrations, Aaron Lindsay, 2018/10/10
- [Qemu-arm] [PATCH v6 08/14] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/10/10
- [Qemu-arm] [PATCH v6 03/14] migration: Add post_save function to VMStateDescription, Aaron Lindsay, 2018/10/10