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[Qemu-commits] [qemu/qemu] f3d9f3: target/ppc: Improve accuracy of guest
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[Qemu-commits] [qemu/qemu] f3d9f3: target/ppc: Improve accuracy of guest HTM availabi... |
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Date: |
Wed, 26 Apr 2017 06:36:16 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f3d9f303acba2fcb97aaa68fdcd4b058c332d0f8
https://github.com/qemu/qemu/commit/f3d9f303acba2fcb97aaa68fdcd4b058c332d0f8
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Improve accuracy of guest HTM availability on P8s
On Power8 hosts it is currently theoretically possible for QEMU/KVM-HV guests
to receive a ibm,pa-features property indicating that HTM support is available
when it is not. The situation would occur if the platform firmware of
a Power8 host cleared the HTM bit of the ibm,pa-features property.
QEMU would query KVM for the availability of HTM, which will return no
support, but workaround code in kvm_arch_init_vcpu() would then
re-enable it because KVM_HV is in use and the processor is P8.
This patch adjusts the workaround in kvm_arch_init_vcpu() so that it does not
enable HTM (in the above case) unless the host kernel indicates to the QEMU
process, via the auxiliary vector, that userspace can use HTM (via the HWCAP2
bit KVM_FEATURE2_HTM).
The reason to use the value from the auxiliary vector is that it is
set based only on what the host kernel found in the ibm,pa-features
HTM bit at boot time.
Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3fa14fbe1310e8980072447ba405571be7a78a5d
https://github.com/qemu/qemu/commit/3fa14fbe1310e8980072447ba405571be7a78a5d
Author: David Gibson <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
pseries: Add pseries-2.10 machine type
Signed-off-by: David Gibson <address@hidden>
Commit: 147ff8079ee0cf45562e202c1054814f14628b65
https://github.com/qemu/qemu/commit/147ff8079ee0cf45562e202c1054814f14628b65
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_rtc.c
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/spapr: QOM'ify sPAPRRTCState
Also use an 'sPAPRRTCState' attribute under the sPAPR machine to hold
the RTC object. Overall, these changes remove an unnecessary and
implicit dependency on SysBus.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9d169fb3c8c8434124677afa52824c4b15b62b65
https://github.com/qemu/qemu/commit/9d169fb3c8c8434124677afa52824c4b15b62b65
Author: Thomas Huth <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
hw/ppc/pnv: Classify the "PowerNV Chip" devices as CPU devices
The devices that are derived from TYPE_PNV_CHIP currently show up
as "uncategorized" devices in the help text of "-device ?". Since
they obviously are related to the CPU, let's put them into the
CPU category instead.
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d6ee2a7c85088d587fb0e0376fba1fa20d59c9f3
https://github.com/qemu/qemu/commit/d6ee2a7c85088d587fb0e0376fba1fa20d59c9f3
Author: Alexey Kardashevskiy <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr_iommu.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target-ppc: kvm: make use of KVM_CREATE_SPAPR_TCE_64
KVM_CAP_SPAPR_TCE capability allows creating TCE tables in KVM which
allows having in-kernel acceleration for H_PUT_TCE_xxx hypercalls.
However it only supports 32bit DMA windows at zero bus offset.
There is a new KVM_CAP_SPAPR_TCE_64 capability which supports 64bit
window size, variable page size and bus offset.
This makes use of the new capability. The kernel headers are already
updated as the kernel support went in to v4.6.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c64abd1f9c732f58181d0a46a0da72168759e77b
https://github.com/qemu/qemu/commit/c64abd1f9c732f58181d0a46a0da72168759e77b
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M include/sysemu/kvm.h
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/kvm.c
Log Message:
-----------
spapr: Add ibm,processor-radix-AP-encodings to the device tree
Use the new ioctl, KVM_PPC_GET_RMMU_INFO, to fetch radix MMU
information from KVM and present the page encodings in the device tree
under ibm,processor-radix-AP-encodings. This provides page size
information to the guest which is necessary for it to use radix mode.
Signed-off-by: Sam Bobroff <address@hidden>
[dwg: Compile fix for 32-bit targets, style nit fix]
Signed-off-by: David Gibson <address@hidden>
Commit: cf1c4cce7c0d53d2a778a4b124d02ea3a84f1663
https://github.com/qemu/qemu/commit/cf1c4cce7c0d53d2a778a4b124d02ea3a84f1663
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target-ppc: support KVM_CAP_PPC_MMU_RADIX, KVM_CAP_PPC_MMU_HASH_V3
Query and cache the value of two new KVM capabilities that indicate
KVM's support for new radix and hash modes of the MMU.
Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d77a98b01575bbbeff87a83f6e7f5ca0ce3aefdb
https://github.com/qemu/qemu/commit/d77a98b01575bbbeff87a83f6e7f5ca0ce3aefdb
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
Log Message:
-----------
target/ppc: Add new H-CALL shells for in memory table translation
The use of the new in memory tables introduced in ISAv3.00 for translation,
also referred to as process tables, requires the introduction of 3 new
H-CALLs; H_REGISTER_PROCESS_TABLE, H_CLEAN_SLB, and H_INVALIDATE_PID.
Add shells for each of these and register them as the hypercall handlers.
Currently they all log an unimplemented hypercall and return H_FUNCTION.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
[dwg: Fix style nits]
Signed-off-by: David Gibson <address@hidden>
Commit: b4db54132ffeadafa9516cc553ba9548e42d42ad
https://github.com/qemu/qemu/commit/b4db54132ffeadafa9516cc553ba9548e42d42ad
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Implement H_REGISTER_PROCESS_TABLE H_CALL
The H_REGISTER_PROCESS_TABLE H_CALL is used by a guest to indicate to the
hypervisor where in memory its process table is and how translation should
be performed using this process table.
Provide the implementation of this H_CALL for a guest.
We first check for invalid flags, then parse the flags to determine the
operation, and then check the other parameters for valid values based on
the operation (register new table/deregister table/maintain registration).
The process table is then stored in the appropriate location and registered
with the hypervisor (if running under KVM), and the LPCR_[UPRT/GTSE] bits
are updated as required.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: Sam Bobroff <address@hidden>
[dwg: Correct missing prototype and uninitialized variable]
Signed-off-by: David Gibson <address@hidden>
Commit: 86d5771a5ab67b72a0d830f0ac8c0420e18b48d8
https://github.com/qemu/qemu/commit/86d5771a5ab67b72a0d830f0ac8c0420e18b48d8
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: move spapr_populate_pa_features()
In the next patch, spapr_fixup_cpu_dt() will need to call
spapr_populate_pa_features() so move it's definition up without making
any other changes.
Signed-off-by: Sam Bobroff <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9fb4541f5803f8d2ba116b12113386e26482ba30
https://github.com/qemu/qemu/commit/9fb4541f5803f8d2ba116b12113386e26482ba30
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr: Enable ISA 3.0 MMU mode selection via CAS
Add the new node, /chosen/ibm,arch-vec-5-platform-support to the
device tree. This allows the guest to determine which modes are
supported by the hypervisor.
Update the option vector processing in h_client_architecture_support()
to handle the new MMU bits. This allows guests to request hash or
radix mode and QEMU to create the guest's HPT at this time if it is
necessary but hasn't yet been done. QEMU will terminate the guest if
it requests an unavailable mode, as required by the architecture.
Extend the ibm,pa-features node with the new ISA 3.0 values
and set the radix bit if KVM supports radix mode. This probably won't
be used directly by guests to determine the availability of radix mode
(that is indicated by the new node added above) but the architecture
requires that it be set when the hardware supports it.
If QEMU is using KVM, and KVM is capable of running in radix mode,
guests can be run in real-mode without allocating a HPT (because KVM
will use a minimal RPT). So in this case, we avoid creating the HPT
at reset time and later (during CAS) create it if it is necessary.
ISA 3.0 guests will now begin to call h_register_process_table(),
which has been added previously.
Signed-off-by: Sam Bobroff <address@hidden>
[dwg: Strip some unneeded prefix from error messages]
Signed-off-by: David Gibson <address@hidden>
Commit: e957f6a9b92439a222ecd4ff1c8cdc9700710c72
https://github.com/qemu/qemu/commit/e957f6a9b92439a222ecd4ff1c8cdc9700710c72
Author: Sam Bobroff <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_ovec.h
Log Message:
-----------
spapr: Workaround for broken radix guests
For a little while around 4.9, Linux kernels that saw the radix bit in
ibm,pa-features would attempt to set up the MMU as if they were a
hypervisor, even if they were a guest, which would cause them to
crash.
Work around this by detecting pre-ISA 3.0 guests by their lack of that
bit in option vector 1, and then removing the radix bit from
ibm,pa-features. Note: This now requires regeneration of that node
after CAS negotiation.
Signed-off-by: Sam Bobroff <address@hidden>
[dwg: Fix style nits]
Signed-off-by: David Gibson <address@hidden>
Commit: 3dc410ae83e6cb76c81ea30a05d62596092b3165
https://github.com/qemu/qemu/commit/3dc410ae83e6cb76c81ea30a05d62596092b3165
Author: Alexey Kardashevskiy <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target-ppc/kvm: Enable in-kernel TCE acceleration for multi-tce
This enables in-kernel handling of H_PUT_TCE_INDIRECT and
H_STUFF_TCE hypercalls. The host kernel support is there since v4.6,
in particular d3695aa4f452
("KVM: PPC: Add support for multiple-TCE hcalls").
H_PUT_TCE is already accelerated and does not need any special enablement.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a01f3432dd005fc3f216fe3e2b88dc986f0474a9
https://github.com/qemu/qemu/commit/a01f3432dd005fc3f216fe3e2b88dc986f0474a9
Author: Alexey Kardashevskiy <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: Warn when RAM page size is not enabled in IOMMU page mask
If a page size used by QEMU is not enabled in the PHB IOMMU page mask,
in-kernel acceleration of TCE handling won't be enabled and performance
might be slower than expected.
This prints a warning if system page size is not enabled. This should
print a warning if huge pages are enabled but sphb.pgsz still uses
the default value of 4K|64K.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c88fa6dd4a7e0c45729b11f338f18f4042df6649
https://github.com/qemu/qemu/commit/c88fa6dd4a7e0c45729b11f338f18f4042df6649
Author: Alexey Kardashevskiy <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: Removed unused include
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ccd531b9c9de9cc497bd718104bf71b44bdbee45
https://github.com/qemu/qemu/commit/ccd531b9c9de9cc497bd718104bf71b44bdbee45
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Add ibm,processor-radix-AP-encodings for TCG
The ibm,processor-radix-AP-encodings device tree property of the cpu node
is used to specify the radix mode supported page sizes of the processor
to the guest os. Contained in the top 3 bits of the msb is the actual
page size (AP) encoding associated with the corresponding radix mode
supported page size. Add this property for a TCG guest, note the TCG code
is capable of translating any format so just add the 4 default page sizes.
The ibm,processor-radix-AP-encodings device tree property is defined as:
One to n cells in ascending order of radix mode supported page sizes
encoded as BE ints (32bit on ppc) in the form:
0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
- 0bxxx -> AP encoding
- 0byyyyyyyyyyyyyyyyyyyyyyyyyyyyy -> supported page size encoded as a shift
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ad5d1add86b9560c22c3fb8718d6a99eabaaed6a
https://github.com/qemu/qemu/commit/ad5d1add86b9560c22c3fb8718d6a99eabaaed6a
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/intc/xics.c
M hw/intc/xics_spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/xics.h
M target/ppc/cpu.h
Log Message:
-----------
ppc/xics: introduce an 'intc' backlink under PowerPCCPU
Today, the ICPState array of the sPAPR machine is indexed with
'cpu_index' of the CPUState. This numbering of CPUs is internal to
QEMU and the guest only knows about what is exposed in the device
tree, that is the 'cpu_dt_id'. This is why sPAPR uses the helper
xics_get_cpu_index_by_dt_id() to do the mapping in a couple of places.
To provide a more generic XICS layer, we need to abstract the IRQ
'server' number and remove any assumption made on its nature. It
should not be used as a 'cpu_index' for lookups like xics_cpu_setup()
and xics_cpu_destroy() do.
To reach that goal, we choose to introduce a generic 'intc' backlink
under PowerPCCPU, and let the machine core init routine do the
ICPState lookup. The resulting object is passed on to xics_cpu_setup()
which does the store under PowerPCCPU. The IRQ 'server' number in XICS
is now generic. sPAPR uses 'cpu_dt_id' and PowerNV will use 'PIR'
number.
This also has the benefit of simplifying the sPAPR hcall routines
which do not need to do any ICPState lookups anymore.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 06747ba6d424e213efcb58578aadd56eb882877a
https://github.com/qemu/qemu/commit/06747ba6d424e213efcb58578aadd56eb882877a
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/intc/xics_spapr.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: move the IRQ server number mapping under the machine
This is the second step to abstract the IRQ 'server' number of the
XICS layer. Now that the prereq cleanups have been done in the
previous patch, we can move down the 'cpu_dt_id' to 'cpu_index'
mapping in the sPAPR machine handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5bc8d26de20ca6befe6390f381cb98120237e4be
https://github.com/qemu/qemu/commit/5bc8d26de20ca6befe6390f381cb98120237e4be
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/intc/xics.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M include/hw/ppc/spapr.h
M include/hw/ppc/xics.h
Log Message:
-----------
spapr: allocate the ICPState object from under sPAPRCPUCore
Today, all the ICPs are created before the CPUs, stored in an array
under the sPAPR machine and linked to the CPU when the core threads
are realized. This modeling brings some complexity when a lookup in
the array is required and it can be simplified by allocating the ICPs
when the CPUs are.
This is the purpose of this proposal which introduces a new 'icp_type'
field under the machine and creates the ICP objects of the right type
(KVM or not) before the PowerPCCPU object are.
This change allows more cleanups : the removal of the icps array under
the sPAPR machine and the removal of the xics_get_cpu_index_by_dt_id()
helper.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 439071a92dc85d67b5b6c55e7d1098dc6c3e8e89
https://github.com/qemu/qemu/commit/439071a92dc85d67b5b6c55e7d1098dc6c3e8e89
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/intc/xics.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/xics: add a realize() handler to ICPStateClass
It will be used by derived classes in PowerNV for customization.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 99285aae1695f77ea55230554f547b66b685e123
https://github.com/qemu/qemu/commit/99285aae1695f77ea55230554f547b66b685e123
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/intc/Makefile.objs
A hw/intc/xics_pnv.c
M include/hw/ppc/xics.h
Log Message:
-----------
ppc/pnv: add a PnvICPState object
This provides a new ICPState object for the PowerNV machine (POWER8).
Access to the Interrupt Management area is done though a memory
region. It contains the registers of the Interrupt Control Presenters
of each thread which are used to accept, return, forward interrupts in
the system.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 36fc6f080056c3779abc195a40cae76bef0f66f1
https://github.com/qemu/qemu/commit/36fc6f080056c3779abc195a40cae76bef0f66f1
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: extend the machine with a XICSFabric interface
A XICSFabric QOM interface is used by the XICS layer to manipulate the
ICP and ICS objects. Let's define the associated handlers for the
PowerNV machine. All handlers should be defined even if there is no
ICS under the PowerNV machine yet.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 47fea43aa3414fcbab270d84de307cce5657166c
https://github.com/qemu/qemu/commit/47fea43aa3414fcbab270d84de307cce5657166c
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: extend the machine with a InterruptStatsProvider interface
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 960fbd29e56866ff7b1f2c6a24082774fd254bda
https://github.com/qemu/qemu/commit/960fbd29e56866ff7b1f2c6a24082774fd254bda
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
Log Message:
-----------
ppc/pnv: create the ICP object under PnvCore
Each thread of a core is linked to an ICP. This allocates a PnvICPState
object before the PowerPCCPU object is realized and lets the XICSFabric
do the store under the 'intc' backlink when xics_cpu_setup() is
called.
This modeling removes the need of maintaining an array of ICP objects
under the PowerNV machine and also simplifies the XICSFabric icp_get()
handler.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5509db4aec13217022d41b131c8216040fb723f1
https://github.com/qemu/qemu/commit/5509db4aec13217022d41b131c8216040fb723f1
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a helper to calculate MMIO addresses registers
Some controllers (ICP, PSI) have a base register address which is
calculated using the chip id.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bf5615e77cbe5518f201a9be96e13bedb6a5b26d
https://github.com/qemu/qemu/commit/bf5615e77cbe5518f201a9be96e13bedb6a5b26d
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add memory regions for the ICP registers
This provides to a PowerNV chip (POWER8) access to the Interrupt
Management area, which contains the registers of the Interrupt Control
Presenters of each thread. These are used to accept, return, forward
interrupts in the system.
This area is modeled with a per-chip container memory region holding
all the ICP registers. Each thread of a chip is then associated with
its ICP registers using a memory subregion indexed by its PIR number
in the overall region.
The device tree is populated accordingly.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 54f59d786c05765bf7410eadd10e88f5579df9e7
https://github.com/qemu/qemu/commit/54f59d786c05765bf7410eadd10e88f5579df9e7
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_psi.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_psi.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add cut down PSI bridge model and hookup external interrupt
The Processor Service Interface (PSI) Controller is one of the engines
of the "Bridge" unit which connects the different interfaces to the
Power Processor.
This adds just enough of the PSI bridge to handle various on-chip and
the one external interrupt. The rest of PSI has to do with the link to
the IBM FSP service processor which we don't plan to emulate (not used
on OpenPower machines).
The ics_get() and ics_resend() handlers of the XICSFabric interface of
the PowerNV machine are now defined to handle the Interrupt Control
Source of PSI. The InterruptStatsProvider interface is also modified
to dump the new ICS.
Originally from Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0722d05ad8516636e3c2e9033cba7d2d27b59624
https://github.com/qemu/qemu/commit/0722d05ad8516636e3c2e9033cba7d2d27b59624
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_occ.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_occ.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Add OCC model stub with interrupt support
The OCC is an on-chip microcontroller based on a ppc405 core used
for various power management tasks. It comes with a pile of additional
hardware sitting on the PIB (aka XSCOM bus). At this point we don't
emulate it (nor plan to do so). However there is one facility which
is provided by the surrounding hardware that we do need, which is the
interrupt generation facility. OPAL uses it to send itself interrupts
under some circumstances and there are other uses around the corner.
So this implement just enough to support this.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - updated for qemu-2.9
- changed the XSCOM interface to fit new model
- QOMified the model ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4a44fd26dbc4e4f78621a71f52dc7952c9e6485d
https://github.com/qemu/qemu/commit/4a44fd26dbc4e4f78621a71f52dc7952c9e6485d
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M default-configs/ppc64-softmmu.mak
Log Message:
-----------
ppc: add IPMI support
OpenPOWER systems use a BT device to communicate with the BMC.
Provide support for it.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8c6fd7f341fd7e414171e09618b496de871da718
https://github.com/qemu/qemu/commit/8c6fd7f341fd7e414171e09618b496de871da718
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ipmi/ipmi_bmc_sim.c
M qemu-options.hx
Log Message:
-----------
ipmi: use a file to load SDRs
The IPMI BMC simulator populates the sdr/sensor tables with a minimal
set of entries (Watchdog). But some qemu platforms might want to use
extra entries for their custom needs.
This patch modifies slighty the initializing routine to take into
account a larger set read from a file. The name of the file to use is
defined through a new 'sdr' property of the simulator device.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Corey Minyard <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 540c07d3453c1a82dd66608bcb2cde79ea91b192
https://github.com/qemu/qemu/commit/540c07d3453c1a82dd66608bcb2cde79ea91b192
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ipmi/ipmi_bmc_sim.c
M qemu-options.hx
Log Message:
-----------
ipmi: provide support for FRUs
This patch provides a simple FRU support for the BMC simulator. FRUs
are loaded from a file which name is specified in the object
properties, each entry having a fixed size, also specified in the
properties. If the file is unknown or not accessible for some reason,
a unique entry of 1024 bytes is created as a default. Just enough to
start some simulation.
These commands complies with the IPMI spec : "34. FRU Inventory Device
Commands".
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Corey Minyard <address@hidden>
[dwg: Folded in subsequent fix to handle NULL filename]
Signed-off-by: David Gibson <address@hidden>
Commit: 7fabcdb942c2eefa3a40f4cc5ebae25cc13f6ddc
https://github.com/qemu/qemu/commit/7fabcdb942c2eefa3a40f4cc5ebae25cc13f6ddc
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ipmi/ipmi_bmc_sim.c
M include/hw/ipmi/ipmi.h
Log Message:
-----------
ipmi: introduce an ipmi_bmc_sdr_find() API
This patch exposes a new IPMI routine to query a sdr entry from the
sdr table maintained by the IPMI BMC simulator. The API is very
similar to the internal sdr_find_entry() routine and should be used
the same way to query one or all sdrs.
A typical use would be to loop on the sdrs to build nodes of a device
tree.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Corey Minyard <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cd60d85ef6a557acd519874827b52517e6fbc523
https://github.com/qemu/qemu/commit/cd60d85ef6a557acd519874827b52517e6fbc523
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ipmi/ipmi_bmc_sim.c
M include/hw/ipmi/ipmi.h
Log Message:
-----------
ipmi: introduce an ipmi_bmc_gen_event() API
It will be used to fill the message buffer with custom events expected
by some systems. Typically, an Open PowerNV platform guest is notified
with an OEM SEL message before a shutdown or a reboot.
Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Corey Minyard <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b88290cd9ea474fea38c4733f365a3cd2519723e
https://github.com/qemu/qemu/commit/b88290cd9ea474fea38c4733f365a3cd2519723e
Author: Anton Blanchard <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/arch_dump.c
Log Message:
-----------
target/ppc: Fix size of struct PPCElfPrstatus
gdb refuses to parse QEMU memory dumps because struct PPCElfPrstatus
is the wrong size. Fix it.
Signed-off-by: Anton Blanchard <address@hidden>
Fixes: e62fbc54d459 ("target-ppc: dump-guest-memory support")
Signed-off-by: David Gibson <address@hidden>
Commit: 71cd4dace9abf51469cfbf6db622124993955f78
https://github.com/qemu/qemu/commit/71cd4dace9abf51469cfbf6db622124993955f78
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: remove the 'nr_servers' field from the machine
xics_system_init() does not need 'nr_servers' anymore as it is only
used to define the 'interrupt-controller' node in the device tree. So
let's just compute the value when calling spapr_dt_xics().
This also gives us an opportunity to simplify the xics_system_init()
routine and introduce a specific spapr_ics_create() helper to create
the sPAPR ICS object.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490
https://github.com/qemu/qemu/commit/4d1df88b63c68f84a3c1a84a7f88cb8e6fa99490
Author: Benjamin Herrenschmidt <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: Add support for POWER8+ LPC Controller
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset
- moved the IRQ handler in pnv_lpc.c
- introduced pnv_lpc_isa_irq_create() to create the ISA IRQs ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7
https://github.com/qemu/qemu/commit/5a7e14a274a6d3d7bc20f2a60037e9a4db97bec7
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
Log Message:
-----------
ppc/pnv: enable only one LPC bus
The default LPC bus of a multichip system is on chip 0. It's
recognized by the firmware (skiboot) using a "primary" property in the
device tree.
We introduce a pnv_chip_lpc_offset() routine to locate the LPC node of
a chip and set the property directly from the machine level.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e7a3fee3407b92ed8411c99206304d45d679d2a5
https://github.com/qemu/qemu/commit/e7a3fee3407b92ed8411c99206304d45d679d2a5
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: scan ISA bus to populate device tree
This is an empty shell that we will use to include nodes in the device
tree for ISA devices. We expect RTC, UART and IPMI BT devices.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c5ffdcaea57f6975e8790e4c1ba242d9e04227e2
https://github.com/qemu/qemu/commit/c5ffdcaea57f6975e8790e4c1ba242d9e04227e2
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: populate device tree for RTC devices
The code could be common to any ISA device but we are missing the IO
length.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cb228f5a00977370796bba2487cbaef2ed26881e
https://github.com/qemu/qemu/commit/cb228f5a00977370796bba2487cbaef2ed26881e
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: populate device tree for serial devices
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 04f6c8b2c001b57b904cb9e2caea774303601253
https://github.com/qemu/qemu/commit/04f6c8b2c001b57b904cb9e2caea774303601253
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: populate device tree for IPMI BT devices
When an ipmi-bt device [1] is defined on the ISA bus, we need to
populate the device tree with the object properties. Such devices are
created with the command line options :
-device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10
[1] https://lists.gnu.org/archive/html/qemu-devel/2015-11/msg03168.html
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: aeaef83dabfec1c1666e65a0c5375983c7a23089
https://github.com/qemu/qemu/commit/aeaef83dabfec1c1666e65a0c5375983c7a23089
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_bmc.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add initial IPMI sensors for the BMC simulator
Skiboot, the firmware for the PowerNV platform, expects the BMC to
provide some specific IPMI sensors. These sensors are exposed in the
device tree and their values are updated by the firmware at boot time.
Sensors of interest are :
"FW Boot Progress"
"Boot Count"
As such a device is defined on the command line, we can only detect
its presence at reset time.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bce0b6915971968e3d00e13af5369f6df3daaeb6
https://github.com/qemu/qemu/commit/bce0b6915971968e3d00e13af5369f6df3daaeb6
Author: Cédric Le Goater <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_bmc.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: generate an OEM SEL event on shutdown
OpenPOWER systems expect to be notified with such an event before a
shutdown or a reboot. An OEM SEL message is sent with specific
identifiers and a user data containing the request : OFF or REBOOT.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8f37e54e5b9960151dfb16183fc1c530a0674c77
https://github.com/qemu/qemu/commit/8f37e54e5b9960151dfb16183fc1c530a0674c77
Author: Bharata B Rao <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr-cpu-core: Release ICPState object during CPU unrealization
Recent commits that re-organized ICPState object missed to destroy
the object when CPU is unrealized. Fix this so that CPU unplug
doesn't abort QEMU.
Signed-off-by: Bharata B Rao <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 31b2b0f8463533c32b5ad76e73668e2e9fca8ae2
https://github.com/qemu/qemu/commit/31b2b0f8463533c32b5ad76e73668e2e9fca8ae2
Author: Suraj Jitindar Singh <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/helper.h
M target/ppc/misc_helper.c
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Flush TLB on write to PIDR
The PIDR (process id register) is used to store the id of the currently
running process, which is used to select the process table entry used to
perform address translation. This means that when we write to this register
all the translations in the TLB become outdated as they are for a
previously running process. Thus when this register is written to we need
to invalidate the TLB entries to ensure stale entries aren't used to
to perform translation for the new process, which would result in at best
segfaults or alternatively just random memory being accessed.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[dwg: Fixed compile error for 32-bit targets]
Signed-off-by: David Gibson <address@hidden>
Commit: b1c897d58729bd5cb390afa4e311dc42b38baf77
https://github.com/qemu/qemu/commit/b1c897d58729bd5cb390afa4e311dc42b38baf77
Author: Bernhard Kaindl <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/translate_init.c
Log Message:
-----------
e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read
This patch registers mfspr 259 for Book3S and e500 family cores
following this research:
mfspr 259 provides read-only mapped user access to SPRG3(SPR 275) according to:
- PowerISA 2.02, Book III (documents implementation starting with POWER4+ @ p20)
- IBM PowerPC 970MP RISC Microprocessor User's Manual v2.1, page 48
- Amit Singh: "Mac OS X Internals: A Systems Approach" on 970 and 970FX cores:
He demonstrates mfspr 259 reading TLS data from Mac OS X on G5 on page 588
- NXP documents it in the Core Reference Manuals of: e500, e500mc and e5500
- getcpu() of the 32 & 64-bit Book3S Linux vDSOs use it to read the core number
mfspr 259 does not appear to be implemented in these cores according to:
- 74xx series: MPC7410/MPC7400 and MPC7450 RISC Microprocessor Reference Manuals
- 4xx series: PPC440 Processor User's Manual, Revision 1.09 by AMCC
- 750 series: IBM PowerPC 750CL RISC Microprocessor User's Manual
- e200 series: e200z4 Power Architectureâ Core Reference Manual
Implementation: gen_spr_usprg3() is called from init_proc_book3s_common()
(covers the 970 and POWER cores) and init_proc_e500() (covers the e500 family)
to register spr_read_ureg() in the same way which it already provides
the mapped SPR access for SPR_USPRG4-7 in gen_spr_usprgh() for cores
which have the same read-only mapped SPRG register access for SPRG4-7.
Verified using Linux by pinning a thread to a core and checking sched_getcpu()
using qemu-system-ppc64 -M pseries -cpu POWER8 using MTTCG on a x86_64 host.
Signed-off-by: Bernhard Kaindl <address@hidden>
Reviewed-by: Stefan Resch <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c364946dd5209d77262aeac3188efc710d9dbb1e
https://github.com/qemu/qemu/commit/c364946dd5209d77262aeac3188efc710d9dbb1e
Author: David Gibson <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M target/ppc/translate_init.c
Log Message:
-----------
target/ppc: Style fixes
This makes a small step fixing one of many style problems that exist in
the older ppc code. This removes spaces between function (or macro) name
and the following '('.
Signed-off-by: David Gibson <address@hidden>
Commit: df02d2ca8b23ba1fff137090a65731c68cf1393d
https://github.com/qemu/qemu/commit/df02d2ca8b23ba1fff137090a65731c68cf1393d
Author: Scott Wood <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Remove myself from e500
I recently left Freescale/NXP, and even before that it'd been a few years
since I was actively involved in KVM/QEMU work.
Signed-off-by: Scott Wood <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dcaed66cbe2803f9378f3a043c2e482bf8035dfd
https://github.com/qemu/qemu/commit/dcaed66cbe2803f9378f3a043c2e482bf8035dfd
Author: Peter Maydell <address@hidden>
Date: 2017-04-26 (Wed, 26 Apr 2017)
Changed paths:
M MAINTAINERS
M default-configs/ppc64-softmmu.mak
M hw/intc/Makefile.objs
M hw/intc/xics.c
A hw/intc/xics_pnv.c
M hw/intc/xics_spapr.c
M hw/ipmi/ipmi_bmc_sim.c
M hw/ppc/Makefile.objs
M hw/ppc/pnv.c
A hw/ppc/pnv_bmc.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_lpc.c
A hw/ppc/pnv_occ.c
A hw/ppc/pnv_psi.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_rtc.c
M include/hw/ipmi/ipmi.h
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_lpc.h
A include/hw/ppc/pnv_occ.h
A include/hw/ppc/pnv_psi.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_ovec.h
M include/hw/ppc/xics.h
M include/sysemu/kvm.h
M qemu-options.hx
M target/ppc/arch_dump.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/helper.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/misc_helper.c
M target/ppc/translate_init.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.10-20170426'
into staging
ppc patch queue 2017-04-26
Here's a respind of my first pull request for qemu-2.10, consisting of
assorted patches which have accumulated while qemu-2.9 stabilized.
Highlights are:
* Rework / cleanup of the XICS interrupt controller
* Substantial improvement to the 'powernv' machine type
- Includes an MMIO XICS version
* POWER9 support improvements
- POWER9 guests with KVM
- Partial support for POWER9 guests with TCG
* IOMMU and VFIO improvements
* Assorted minor changes
There are several IPMI patches here that aren't usually in my area of
maintenance, but there isn't a regular maintainer and these patches
are for the benefit of the powernv machine type.
This pull request supersedes my 2017-04-26 pull request. This new set
fixes a bug in one of the aforementioned IPMI patches which caused
clang sanitizer failures (and may have crashed on some libc / host
versions).
# gpg: Signature made Wed 26 Apr 2017 07:58:10 BST
# gpg: using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-2.10-20170426: (48 commits)
MAINTAINERS: Remove myself from e500
target/ppc: Style fixes
e500,book3s: mfspr 259: Register mapped/aliased SPRG3 user read
target/ppc: Flush TLB on write to PIDR
spapr-cpu-core: Release ICPState object during CPU unrealization
ppc/pnv: generate an OEM SEL event on shutdown
ppc/pnv: add initial IPMI sensors for the BMC simulator
ppc/pnv: populate device tree for IPMI BT devices
ppc/pnv: populate device tree for serial devices
ppc/pnv: populate device tree for RTC devices
ppc/pnv: scan ISA bus to populate device tree
ppc/pnv: enable only one LPC bus
ppc/pnv: Add support for POWER8+ LPC Controller
spapr: remove the 'nr_servers' field from the machine
target/ppc: Fix size of struct PPCElfPrstatus
ipmi: introduce an ipmi_bmc_gen_event() API
ipmi: introduce an ipmi_bmc_sdr_find() API
ipmi: provide support for FRUs
ipmi: use a file to load SDRs
ppc: add IPMI support
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/52e94ea5de3e...dcaed66cbe28
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