[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 23b7aa: tcg/aarch64: Introduce and use long b
From: |
GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] 23b7aa: tcg/aarch64: Introduce and use long branch to regi... |
Date: |
Mon, 10 Jul 2017 06:06:25 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 23b7aa1d2af04ba57cc94f74d9f0ab25dce72fa0
https://github.com/qemu/qemu/commit/23b7aa1d2af04ba57cc94f74d9f0ab25dce72fa0
Author: Pranith Kumar <address@hidden>
Date: 2017-07-09 (Sun, 09 Jul 2017)
Changed paths:
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: Introduce and use long branch to register
We can use a branch to register instruction for exit_tb for offsets
greater than 128MB.
CC: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: b68686bd4bfeb70040b4099df993dfa0b4f37b03
https://github.com/qemu/qemu/commit/b68686bd4bfeb70040b4099df993dfa0b4f37b03
Author: Pranith Kumar <address@hidden>
Date: 2017-07-09 (Sun, 09 Jul 2017)
Changed paths:
M accel/tcg/translate-all.c
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: Use ADRP+ADD to compute target address
We use ADRP+ADD to compute the target address for goto_tb. This patch
introduces the NOP instruction which is used to align the above
instruction pair so that we can use one atomic instruction to patch
the destination offsets.
CC: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 2acee8b2b5e6bba2935bb6ce5be92d0f0f9799cb
https://github.com/qemu/qemu/commit/2acee8b2b5e6bba2935bb6ce5be92d0f0f9799cb
Author: Pranith Kumar <address@hidden>
Date: 2017-07-09 (Sun, 09 Jul 2017)
Changed paths:
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: Enable indirect jump path using LDR (literal)
This patch enables the indirect jump path using an LDR (literal)
instruction. It will be interesting to test and see which performs
better among the two paths.
CC: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 2ae96c157ab3155baf6595c08cf5d3fe3c023a60
https://github.com/qemu/qemu/commit/2ae96c157ab3155baf6595c08cf5d3fe3c023a60
Author: Pranith Kumar <address@hidden>
Date: 2017-07-09 (Sun, 09 Jul 2017)
Changed paths:
M util/cacheinfo.c
Log Message:
-----------
util/cacheinfo: Fix warning generated by clang
Clang generates the following warning on aarch64 host:
CC util/cacheinfo.o
/home/pranith/qemu/util/cacheinfo.c:121:48: warning: value size does not match
register size specified by the constraint and modifier [-Wasm-operand-widths]
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^
/home/pranith/qemu/util/cacheinfo.c:121:28: note: use constraint modifier "w"
asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
^~
%w0
Constraint modifier 'w' is not (yet?) accepted by gcc. Fix this by increasing
the ctr size.
Tested-by: Emilio G. Cota <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 8b8d768f19037a825a0bc81654492caa7c8fab8b
https://github.com/qemu/qemu/commit/8b8d768f19037a825a0bc81654492caa7c8fab8b
Author: Jiang Biao <address@hidden>
Date: 2017-07-09 (Sun, 09 Jul 2017)
Changed paths:
M tcg/mips/tcg-target.inc.c
Log Message:
-----------
tcg/mips: Bugfix for crash when running program with qemu-i386.
When running a helloworld program with qemu-i386 in linux-user
mode on Loongson 3A3000, it will crash. This patch fix the bug.
Signed-off-by: Jiang Biao <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 6580476a14ae0db300733d8b9991fd937cf5e703
https://github.com/qemu/qemu/commit/6580476a14ae0db300733d8b9991fd937cf5e703
Author: Peter Maydell <address@hidden>
Date: 2017-07-10 (Mon, 10 Jul 2017)
Changed paths:
M accel/tcg/translate-all.c
M tcg/aarch64/tcg-target.inc.c
M tcg/mips/tcg-target.inc.c
M util/cacheinfo.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170709' into staging
Queued TCG patches
# gpg: Signature made Mon 10 Jul 2017 08:31:44 BST
# gpg: using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
# gpg: aka "Richard Henderson <address@hidden>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B
* remotes/rth/tags/pull-tcg-20170709:
tcg/mips: Bugfix for crash when running program with qemu-i386.
util/cacheinfo: Fix warning generated by clang
tcg/aarch64: Enable indirect jump path using LDR (literal)
tcg/aarch64: Use ADRP+ADD to compute target address
tcg/aarch64: Introduce and use long branch to register
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/77d472291812...6580476a14ae
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 23b7aa: tcg/aarch64: Introduce and use long branch to regi...,
GitHub <=