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[Qemu-commits] [qemu/qemu] 1f1637: target/arm: Add "ARM_CP_NO_GDB" as a
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GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] 1f1637: target/arm: Add "ARM_CP_NO_GDB" as a new bit field... |
Date: |
Fri, 18 May 2018 11:48:08 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 1f16378718fa87d63f70d0797f4546a88d8e3dd7
https://github.com/qemu/qemu/commit/1f16378718fa87d63f70d0797f4546a88d8e3dd7
Author: Abdallah Bouassida <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type
This is a preparation for the coming feature of creating dynamically an XML
description for the ARM sysregs.
A register has ARM_CP_NO_GDB enabled will not be shown in the dynamic XML.
This bit is enabled automatically when creating CP_ANY wildcard aliases.
This bit could be enabled manually for any register we want to remove from the
dynamic XML description.
Signed-off-by: Abdallah Bouassida <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9c513e786d85cc58b8ba56a482566f759e0835b6
https://github.com/qemu/qemu/commit/9c513e786d85cc58b8ba56a482566f759e0835b6
Author: Abdallah Bouassida <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add "_S" suffix to the secure version of a sysreg
This is a preparation for the coming feature of creating dynamically an XML
description for the ARM sysregs.
Add "_S" suffix to the secure version of sysregs that have both S and NS views
Replace (S) and (NS) by _S and _NS for the register that are manually defined,
so all the registers follow the same convention.
Signed-off-by: Abdallah Bouassida <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 200bf5b7ffea635079cc05fdfb363372b9544ce7
https://github.com/qemu/qemu/commit/200bf5b7ffea635079cc05fdfb363372b9544ce7
Author: Abdallah Bouassida <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M gdbstub.c
M include/qom/cpu.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Add the XML dynamic generation
Generate an XML description for the cp-regs.
Register these regs with the gdb_register_coprocessor().
Add arm_gdb_get_sysreg() to use it as a callback to read those regs.
Add a dummy arm_gdb_set_sysreg().
Signed-off-by: Abdallah Bouassida <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 22cd0945b8429f818a2d90f06f02bb526bfb319d
https://github.com/qemu/qemu/commit/22cd0945b8429f818a2d90f06f02bb526bfb319d
Author: Francisco Iglesias <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M hw/dma/Makefile.objs
A hw/dma/xlnx-zdma.c
A include/hw/dma/xlnx-zdma.h
Log Message:
-----------
xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA
Add a model of the generic DMA found on Xilinx ZynqMP.
Signed-off-by: Francisco Iglesias <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 04965bca4e659a78a73fb0de2bc394fc04282a70
https://github.com/qemu/qemu/commit/04965bca4e659a78a73fb0de2bc394fc04282a70
Author: Francisco Iglesias <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M hw/arm/xlnx-zynqmp.c
M include/hw/arm/xlnx-zynqmp.h
Log Message:
-----------
xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA
The ZynqMP contains two instances of a generic DMA, the GDMA, located in the
FPD (full power domain), and the ADMA, located in LPD (low power domain). This
patch adds these two DMAs to the ZynqMP board.
Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 24af32e049684827286e24114a066e09d0dcdaaf
https://github.com/qemu/qemu/commit/24af32e049684827286e24114a066e09d0dcdaaf
Author: Eric Auger <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event
Coverity complains about use of uninitialized Evt struct.
The EVT_SET_TYPE and similar setters use deposit32() on fields
in the struct, so they read the uninitialized existing values.
In cases where we don't set all the fields in the event struct
we'll end up leaking random uninitialized data from QEMU's
stack into the guest.
Initializing the struct with "Evt evt = {};" ought to satisfy
Coverity and fix the data leak.
Signed-off-by: Eric Auger <address@hidden>
Reported-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 118eee6ceeaa2b6dd007115ec65ae486e4dee4ed
https://github.com/qemu/qemu/commit/118eee6ceeaa2b6dd007115ec65ae486e4dee4ed
Author: Eric Auger <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M hw/arm/smmu-common.c
Log Message:
-----------
hw/arm/smmu-common: Fix coverity issue in get_block_pte_address
Coverity points out that this can overflow if n > 31,
because it's only doing 32-bit arithmetic. Let's use 1ULL instead
of 1. Also the formulae used to compute n can be replaced by
the level_shift() macro.
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 8c71baedb8055beaa681823206ee3a74f9f8649a
https://github.com/qemu/qemu/commit/8c71baedb8055beaa681823206ee3a74f9f8649a
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/translate-a64.c
A target/arm/translate-a64.h
Log Message:
-----------
target/arm: Introduce translate-a64.h
Move some stuff that will be common to both translate-a64.c
and translate-sve.c.
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 38388f7ee3adc04a7e7246c04352451c4f8d00fb
https://github.com/qemu/qemu/commit/38388f7ee3adc04a7e7246c04352451c4f8d00fb
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M .gitignore
M target/arm/Makefile.objs
A target/arm/sve.decode
M target/arm/translate-a64.c
A target/arm/translate-sve.c
Log Message:
-----------
target/arm: Add SVE decode skeleton
Including only 4, as-yet unimplemented, instruction patterns
so that the whole thing compiles.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 39eea56172e668cc4cca611ed9166779df54ac63
https://github.com/qemu/qemu/commit/39eea56172e668cc4cca611ed9166779df54ac63
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Bitwise Logical - Unpredicated Group
These were the instructions that were stubbed out when
introducing the decode skeleton.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d1822297f63b68c1fd8c5282b753d00c95701dd8
https://github.com/qemu/qemu/commit/d1822297f63b68c1fd8c5282b753d00c95701dd8
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE load vector/predicate
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9e18d7a67fa6be84d14fc72deaf00bb6b28d8b7e
https://github.com/qemu/qemu/commit/9e18d7a67fa6be84d14fc72deaf00bb6b28d8b7e
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/Makefile.objs
A target/arm/helper-sve.h
M target/arm/helper.h
M target/arm/sve.decode
A target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE predicate test
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 516e246a1a292f6c6f6aad5451799accbb08acd9
https://github.com/qemu/qemu/commit/516e246a1a292f6c6f6aad5451799accbb08acd9
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Predicate Logical Operations Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 028e2a7b876631eff165cac59eb43bdb2dcc213b
https://github.com/qemu/qemu/commit/028e2a7b876631eff165cac59eb43bdb2dcc213b
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Predicate Misc Group
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f97cfd596ed9bd38644323cb61d19b85ac703c81
https://github.com/qemu/qemu/commit/f97cfd596ed9bd38644323cb61d19b85ac703c81
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 047cec971d2791b206677b954227ea92ff7ee3db
https://github.com/qemu/qemu/commit/047cec971d2791b206677b954227ea92ff7ee3db
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Reduction Group
Excepting MOVPRFX, which isn't a reduction. Presumably it is
placed within the group because of its encoding.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: ccd841c3d71db6943f8b6d3d56bd2abb548ba40c
https://github.com/qemu/qemu/commit/ccd841c3d71db6943f8b6d3d56bd2abb548ba40c
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE bitwise shift by immediate (predicated)
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 27721dbb7ae5e2a52f06588cf38854e4cbc613c0
https://github.com/qemu/qemu/commit/27721dbb7ae5e2a52f06588cf38854e4cbc613c0
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE bitwise shift by vector (predicated)
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7
https://github.com/qemu/qemu/commit/fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE bitwise shift by wide elements (predicated)
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: afac6d0467c1327ad2e30a3c35347fcf5a773742
https://github.com/qemu/qemu/commit/afac6d0467c1327ad2e30a3c35347fcf5a773742
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 96a36e4a44bbf296ac212ed68ebf4e48d3dfb1f0
https://github.com/qemu/qemu/commit/96a36e4a44bbf296ac212ed68ebf4e48d3dfb1f0
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Multiply-Add Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: fea98f9c3077e4666f6d4933030b5891fbd6bb12
https://github.com/qemu/qemu/commit/fea98f9c3077e4666f6d4933030b5891fbd6bb12
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9a56c9c3a955b77fe436beef7ac03c76a65fa32d
https://github.com/qemu/qemu/commit/9a56c9c3a955b77fe436beef7ac03c76a65fa32d
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Index Generation Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 96f922ccccb08c7725c1276ac87697f5dff69edf
https://github.com/qemu/qemu/commit/96f922ccccb08c7725c1276ac87697f5dff69edf
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Stack Allocation Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d9d78dccc86eed10ccf1c8e1ac236e41ec330b06
https://github.com/qemu/qemu/commit/d9d78dccc86eed10ccf1c8e1ac236e41ec330b06
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Bitwise Shift - Unpredicated Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4b242d9c1b6beaf5c81d84e956243b614a4a1d84
https://github.com/qemu/qemu/commit/4b242d9c1b6beaf5c81d84e956243b614a4a1d84
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Compute Vector Address Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0762cd428fd7b471207f5cb5b4bd4bd8f141dbe0
https://github.com/qemu/qemu/commit/0762cd428fd7b471207f5cb5b4bd4bd8f141dbe0
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE floating-point exponential accelerator
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: a1f233f25fd502f9a5b40c14df1b4dbdda463487
https://github.com/qemu/qemu/commit/a1f233f25fd502f9a5b40c14df1b4dbdda463487
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE floating-point trig select coefficient
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 24e82e68341e73ec0f65534c78c13fd03395b188
https://github.com/qemu/qemu/commit/24e82e68341e73ec0f65534c78c13fd03395b188
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Element Count Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: e1fa1164f397bbd381439ed32d97d9b4b4d7eb43
https://github.com/qemu/qemu/commit/e1fa1164f397bbd381439ed32d97d9b4b4d7eb43
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Bitwise Immediate Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f25a2361539626721dbccce14c077cad03b2e72c
https://github.com/qemu/qemu/commit/f25a2361539626721dbccce14c077cad03b2e72c
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Integer Wide Immediate - Predicated Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b94f8f60bd841c5b737185cd38263e26822f77ab
https://github.com/qemu/qemu/commit/b94f8f60bd841c5b737185cd38263e26822f77ab
Author: Richard Henderson <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SVE Permute - Extract Group
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5bcf917ee37a5efbef99f091a96db54a5276becb
https://github.com/qemu/qemu/commit/5bcf917ee37a5efbef99f091a96db54a5276becb
Author: Peter Maydell <address@hidden>
Date: 2018-05-18 (Fri, 18 May 2018)
Changed paths:
M .gitignore
M gdbstub.c
M hw/arm/smmu-common.c
M hw/arm/smmuv3.c
M hw/arm/xlnx-zynqmp.c
M hw/dma/Makefile.objs
A hw/dma/xlnx-zdma.c
M include/hw/arm/xlnx-zynqmp.h
A include/hw/dma/xlnx-zdma.h
M include/qom/cpu.h
M target/arm/Makefile.objs
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub.c
A target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
A target/arm/sve.decode
A target/arm/sve_helper.c
M target/arm/translate-a64.c
A target/arm/translate-a64.h
A target/arm/translate-sve.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180518'
into staging
target-arm queue:
* Initial part of SVE implementation (currently disabled)
* smmuv3: fix some minor Coverity issues
* add model of Xilinx ZynqMP generic DMA controller
* expose (most) Arm coprocessor/system registers to
gdb via QEMU's gdbstub, for reads only
# gpg: Signature made Fri 18 May 2018 18:18:27 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180518: (32 commits)
target/arm: Implement SVE Permute - Extract Group
target/arm: Implement SVE Integer Wide Immediate - Predicated Group
target/arm: Implement SVE Bitwise Immediate Group
target/arm: Implement SVE Element Count Group
target/arm: Implement SVE floating-point trig select coefficient
target/arm: Implement SVE floating-point exponential accelerator
target/arm: Implement SVE Compute Vector Address Group
target/arm: Implement SVE Bitwise Shift - Unpredicated Group
target/arm: Implement SVE Stack Allocation Group
target/arm: Implement SVE Index Generation Group
target/arm: Implement SVE Integer Arithmetic - Unpredicated Group
target/arm: Implement SVE Integer Multiply-Add Group
target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group
target/arm: Implement SVE bitwise shift by wide elements (predicated)
target/arm: Implement SVE bitwise shift by vector (predicated)
target/arm: Implement SVE bitwise shift by immediate (predicated)
target/arm: Implement SVE Integer Reduction Group
target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group
target/arm: Implement SVE Predicate Misc Group
target/arm: Implement SVE Predicate Logical Operations Group
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/d32e41a1188e...5bcf917ee37a
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