[Qemu-commits] [qemu/qemu] 681431: ppc440_pcix: Fix a typo in setting a

qemu-commits
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 681431: ppc440_pcix: Fix a typo in setting a

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 681431: ppc440_pcix: Fix a typo in setting a register (Cov...
Date:	Tue, 12 Jun 2018 07:34:11 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 681431893e7c2414825aa3f5265368adbe005dae
      
https://github.com/qemu/qemu/commit/681431893e7c2414825aa3f5265368adbe005dae
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/ppc440_pcix.c

  Log Message:
  -----------
  ppc440_pcix: Fix a typo in setting a register (Coverity CID1390577)

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 56e7404bc19c8abfe02c08f733ad387b58817f94
      
https://github.com/qemu/qemu/commit/56e7404bc19c8abfe02c08f733ad387b58817f94
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/macio/macio.c
    M hw/misc/macio/trace-events

  Log Message:
  -----------
  macio: add trace-events to timer device

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 45fefe7c4d9bfc5a4a222d3d2c8244531e87130f
      
https://github.com/qemu/qemu/commit/45fefe7c4d9bfc5a4a222d3d2c8244531e87130f
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/pci-host/uninorth.c
    M include/hw/pci-host/uninorth.h

  Log Message:
  -----------
  uninorth: remove token register from uninorth device

>From observation of various OS sources it can be seen that the token register
introduced in 4e46dcdbd3 "PPC: Newworld: Add uninorth token register" is not
required, since the only register currently implemented is the uninorth hardware
version which is read-only.

Remove the token register implementation and instead return the uninorth
version corresponding to the hardware.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: e20c63140a185c166e91d8c68a2aa6bb99e600c3
      
https://github.com/qemu/qemu/commit/e20c63140a185c166e91d8c68a2aa6bb99e600c3
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr_drc.c

  Log Message:
  -----------
  hw/ppc/spapr_drc: Replace error_setg(&error_abort) by error_report() + abort()

Use error_report() + abort() instead of error_setg(&error_abort),
as suggested by the "qapi/error.h" documentation:

    Please don't error_setg(&error_fatal, ...), use error_report() and
    exit(), because that's more obvious.
    Likewise, don't error_setg(&error_abort, ...), use assert().

Use abort() instead of the suggested assert() because the error message
already got displayed.

Suggested-by: Eric Blake <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 31085338293a1203187c6ef6dba9dfce14021189
      
https://github.com/qemu/qemu/commit/31085338293a1203187c6ef6dba9dfce14021189
  Author: Thomas Huth <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use proper logging function for possible guest errors

fprintf() and qemu_log_separate() are frowned upon these days for printing
logging information in QEMU. Accessing the wrong SPRs indicates wrong guest
behaviour in most cases, and we've got a proper way to log such situations,
which is the qemu_log_mask(LOG_GUEST_ERROR, ...) function. So use this
function now for logging the bad SPR accesses instead.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 875bad313580f99cc9642d2941d0dbeeadf4ef25
      
https://github.com/qemu/qemu/commit/875bad313580f99cc9642d2941d0dbeeadf4ef25
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/prep.c

  Log Message:
  -----------
  40p: remove pci_allow_0_address = true from 40p machine class

The Linux sandalfoot zImage has an initialisation process which resets the
VGA controller by setting all the BAR addresses to zero to access the VGA
ioports at their legacy addresses.

Unfortunately setting the framebuffer BAR to address 0 makes the framebuffer
memory overlap the internal VGA memory causing accesses to fail, and so
prevents the kernel from switching successfully to text mode.

Since OpenHackWare configures the framebuffer BAR address outside of the legacy
VGA internal memory space, remove pci_allow_0_address from the 40p machine class
which causes the BAR reprogramming to zero to fail and so the VGA internal
memory can be accessed correctly again.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7cb00357c155240bae3b17eaa00415087b004c52
      
https://github.com/qemu/qemu/commit/7cb00357c155240bae3b17eaa00415087b004c52
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/prep.c

  Log Message:
  -----------
  prep: fix keyboard for the 40p machine

Commit 72d3d8f052 "hw/isa/superio: Add a keyboard/mouse controller (8042)"
added an 8042 keyboard device to the PC87312 superio device to replace that
being used by the prep machine.

Unfortunately this commit didn't do the same for the 40p machine which broke
the keyboard by registering two 8042 keyboard devices at the same address.

Resolve this by similarly removing the 8042 keyboard from the 40p machine as
done for the prep machine in commit 72d3d8f052.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8fea70440eb0d095442de7e80d586a285cf96be5
      
https://github.com/qemu/qemu/commit/8fea70440eb0d095442de7e80d586a285cf96be5
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc: Factor out the parsing in kvmppc_get_cpu_characteristics()

Factor out the parsing of struct kvm_ppc_cpu_char in
kvmppc_get_cpu_characteristics() into a separate function for each cap
for simplicity.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6b37554458a1e8cfe8f91ef0beac82e8de8f85bb
      
https://github.com/qemu/qemu/commit/6b37554458a1e8cfe8f91ef0beac82e8de8f85bb
  Author: Joel Stanley <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M target/ppc/helper.h
    M target/ppc/misc_helper.c
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  target/ppc: Allow privileged access to SPR_PCR

The powerpc Linux kernel[1] and skiboot firmware[2] recently gained changes
that cause the Processor Compatibility Register (PCR) SPR to be cleared.

These changes cause Linux to fail to boot on the Qemu powernv machine
with an error:

 Trying to write privileged spr 338 (0x152) at 0000000030017f0c

With this patch Qemu makes this register available as a hypervisor
privileged register.

Note that bits set in this register disable features of the processor.
Currently the only register state that is supported is when the register
is zeroed (enable all features). This is sufficient for guests to
once again boot.

[1] https://lkml.kernel.org/r/address@hidden
[2] https://patchwork.ozlabs.org/patch/915932/

Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: efe2add7cb7f870ebd90ac4f9637161a4821200a
      
https://github.com/qemu/qemu/commit/efe2add7cb7f870ebd90ac4f9637161a4821200a
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr_vio.c
    M qemu-doc.texi

  Log Message:
  -----------
  spapr/vio: deprecate the "irq" property

VIO devices have an "irq" property that can be used by the sPAPR IRQ
allocator as an IRQ number hint. But it is not set in QEMU nor in
libvirt. It brings unnecessary complexity to the underlying layers
managing the IRQ number space and it is in full opposition with the
new static IRQ allocator we want to introduce in sPAPR.

Let's deprecate it to simplify the spapr_irq_alloc routine in the
future.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
[dwg: Check qtest_enabled() to suppress bogus warnings from make check]
Signed-off-by: David Gibson <address@hidden>


  Commit: 0c1272cc7c72dfe0ef66be8f283cf67c74b58586
      
https://github.com/qemu/qemu/commit/0c1272cc7c72dfe0ef66be8f283cf67c74b58586
  Author: Nicholas Piggin <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M include/qemu/osdep.h

  Log Message:
  -----------
  osdep: powerpc64 align memory to allow 2MB radix THP page tables

This allows KVM with the Book3S radix MMU mode to take advantage of
THP and install larger pages in the partition scope page tables (the
host translation).

Signed-off-by: Nicholas Piggin <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eba45926c2dfb64000da7f83b253f935d6d77941
      
https://github.com/qemu/qemu/commit/eba45926c2dfb64000da7f83b253f935d6d77941
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add an entry for the MacIO device headers

Missed while moved in 7092e84d42b.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6ba1647664efc0d7295c03ad4295df403853c70f
      
https://github.com/qemu/qemu/commit/6ba1647664efc0d7295c03ad4295df403853c70f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add entries for the MOS6522 VIA device

Introduced in 51f233ec92c.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c9bca798447879ee1288a469604cf824bc2a4622
      
https://github.com/qemu/qemu/commit/c9bca798447879ee1288a469604cf824bc2a4622
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/mos6522.c

  Log Message:
  -----------
  hw/misc/mos6522: Add trailing '\n' to qemu_log() calls

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a72fed214a9a9503764fc6f62eea17dd09cb487a
      
https://github.com/qemu/qemu/commit/a72fed214a9a9503764fc6f62eea17dd09cb487a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/mac.h

  Log Message:
  -----------
  ppc: remove obsolete pci_pmac_init() definitions from mac.h

Commits 7b19318bee and 8ce3f743c7 removed the pci_pmac_init() and
pci_pmac_u3_init() functions but missed the header prototypes in mac.h. Remove
them since they are no longer needed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4558fadaf550c0bf3c2284f353439a1cdbc407f1
      
https://github.com/qemu/qemu/commit/4558fadaf550c0bf3c2284f353439a1cdbc407f1
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/mac.h

  Log Message:
  -----------
  ppc: remove obsolete macio_init() definition from mac.h

Commits b6712ea391 removed the macio_init() function but missed the header
prototype in mac.h. Remove it since it is no longer needed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 5b64db9754bde0b8e0329ce77d3647a0a2f6da56
      
https://github.com/qemu/qemu/commit/5b64db9754bde0b8e0329ce77d3647a0a2f6da56
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M include/hw/ppc/ppc.h

  Log Message:
  -----------
  ppc: add missing FW_CFG_PPC_NVRAM_FLAT definition

This is used in OpenBIOS to define the memory layout of the NVRAM device. Whilst
currently left at its default value, add the missing definition to ensure it is
reserved.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 72ee08cf4f2d4443d198b4e9f7a6fa2beb06dd6b
      
https://github.com/qemu/qemu/commit/72ee08cf4f2d4443d198b4e9f7a6fa2beb06dd6b
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/mos6522.c

  Log Message:
  -----------
  mos6522: fix vmstate_mos6522_timer version in vmstate_mos6522

This was accidentally introduced when extracting the 6522 VIA functionality
from the CUDA device, and prevents loadvm from completing successfully.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2e3e5c7e92452900e2bb5143c5fb6d47c0897a34
      
https://github.com/qemu/qemu/commit/2e3e5c7e92452900e2bb5143c5fb6d47c0897a34
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/macio/cuda.c
    M hw/misc/mos6522.c
    M include/hw/misc/macio/cuda.h
    M include/hw/misc/mos6522.h

  Log Message:
  -----------
  cuda: embed mos6522_cuda device directly rather than using QOM object link

Examining the migration stream it can be seen that the mos6522 device state is
being stored separately rather than as part of the CUDA device which is
incorrect (and likely to cause issues if another mos6522 device is added to
the machine).

Resolve this by embedding the mos6522_cuda device directly within the CUDA
device rather than using a QOM object link to reference the device separately.

Note that we also bump the version in vmstate_cuda to reflect this change: this
isn't particularly important for the moment as the Mac machine migration isn't
100% reliable due to issues migrating the timebase under TCG.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d638fd5c9681dbb8915147365520888c64f39dac
      
https://github.com/qemu/qemu/commit/d638fd5c9681dbb8915147365520888c64f39dac
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/macio/cuda.c
    M hw/misc/mos6522.c
    M include/hw/misc/mos6522.h

  Log Message:
  -----------
  mos6522: move timer frequency initialisation to mos6522_reset

The 6522 VIA timer frequency cannot be set by altering registers within the
device itself and hence it is a fixed property of the machine.

Move the initialisation of the timer frequency to the mos6522 reset function
and ensure that any subclasses always call the parent reset function so that
it isn't required to store the timer frequency within vmstate_mos6522_timer
itself.

By moving the frequency initialisation to the device reset function then we
find that the realize function for both mos6522 and mos6522_cuda becomes
obsolete and can simply be removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3431bdf5a3c3bd732f78b0433471c2b1cb373564
      
https://github.com/qemu/qemu/commit/3431bdf5a3c3bd732f78b0433471c2b1cb373564
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/misc/mos6522.c

  Log Message:
  -----------
  mos6522: convert VMSTATE_TIMER_PTR_TEST to VMSTATE_TIMER_PTR

The timers are configured in the mos6522 init function and therefore will
always exist, so the function can never return false.

Peter also pointed out that this is the only remaining user of
VMSTATE_TIMER_PTR_TEST in the codebase, so we might as well just convert it
over to VMSTATE_TIMER_PTR and remove mos6522_timer_exist() as it is no
longer required.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: c8fd8373e42821984400382cd91b8bf4e7c14e3b
      
https://github.com/qemu/qemu/commit/c8fd8373e42821984400382cd91b8bf4e7c14e3b
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: extend eieio for POWER9

POWER9 introduced a new variant of the eieio instruction using bit 6
as a hint to tell the CPU it is a store-forwarding barrier.

The usage of this eieio extension was recently added in Linux 4.17
which activated the "support for a store forwarding barrier at kernel
entry/exit".

Unfortunately, it is not possible to insert this new eieio instruction
without considerable change in ppc_tr_translate_insn(). So instead we
loosen the QEMU eieio instruction mask and modify the gen_eieio()
helper to test for bit6. On non-POWER9 CPUs, the bit6 is just ignored
but a warning is emitted as this is not an instruction software should
be using.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 42a907e83921ff2c4f5e6ca9fa6aa6791b43a73f
      
https://github.com/qemu/qemu/commit/42a907e83921ff2c4f5e6ca9fa6aa6791b43a73f
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/i2c/ppc4xx_i2c.c

  Log Message:
  -----------
  ppc4xx_i2c: Clean up and improve error logging

Make it more readable by converting register indexes to decimal
(avoids lot of superfluous 0x0) and distinguish errors caused by
accessing non-existent vs. unimplemented registers.
No functional change.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bfda32a87bc77b9fac83f6c2789d65585115970d
      
https://github.com/qemu/qemu/commit/bfda32a87bc77b9fac83f6c2789d65585115970d
  Author: luporl <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  target/ppc: Allow PIR read in privileged mode

According to PowerISA, the PIR register should be readable in privileged
mode also, not only in hypervisor privileged mode.

PowerISA 3.0 - 4.3.3 Processor Identification Register

"Read access to the PIR is privileged; write access is not provided."

Figure 18 in section 4.4.4 explicitly confirms that mfspr PIR is privileged
and doesn't require hypervisor state.

Cc: David Gibson <address@hidden>
Cc: Alexander Graf <address@hidden>
Cc: address@hidden
Signed-off-by: Leandro Lupori <address@hidden>
Reviewed-by: Jose Ricardo Ziviani <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: fcc8ef17e264ef6f4afb6fa4af71b88993f49363
      
https://github.com/qemu/qemu/commit/fcc8ef17e264ef6f4afb6fa4af71b88993f49363
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: no need to verify the node

The node property can always be queried and the value has already been
verified in pc_dimm_realize().

Acked-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 81985f3be9679b8770f46f78d475ff53a2e8cdbb
      
https://github.com/qemu/qemu/commit/81985f3be9679b8770f46f78d475ff53a2e8cdbb
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: move lookup of the node into spapr_memory_plug()

Let's clean the hotplug handler up by moving lookup of the node into
the function where it is actually being used.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4e8a01bdb20557ee4f5bf6f86890d2b95fa2a7fb
      
https://github.com/qemu/qemu/commit/4e8a01bdb20557ee4f5bf6f86890d2b95fa2a7fb
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: move memory hotplug support check into spapr_memory_pre_plug()

Let's finish cleaning up the hotplug handler. This check can be
performed in the pre_plug code as the very first thing.

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 88432f44aae752028103408f2f6df8c681143907
      
https://github.com/qemu/qemu/commit/88432f44aae752028103408f2f6df8c681143907
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: introduce machine unplug handler

We'll be handling unplug of e.g. CPUs and PCDIMMs  via the general
hotplug handler soon, so let's add that handler function.

Acked-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3ec71474cad1066865b3c2059add208794a418da
      
https://github.com/qemu/qemu/commit/3ec71474cad1066865b3c2059add208794a418da
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: handle pc-dimm unplug via hotplug handler chain

Factor out memory unplug into separate function from spapr_lmb_release().
Then use generic hotplug_handler_unplug() to trigger memory unplug,
which will call spapr_machine_device_unplug() -> spapr_memory_unplug()
in the end.

This way unplug operation is not buried in lmb internals and located in
the same place like in other targets, following similar logic/call chain
across targets.

Acked-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a4261be17213eea96673fac71bc89f5342422b76
      
https://github.com/qemu/qemu/commit/a4261be17213eea96673fac71bc89f5342422b76
  Author: David Hildenbrand <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: handle cpu core unplug via hotplug handler chain

Factor out cpu core unplug into separate function from
spapr_core_release(). Then use generic hotplug_handler_unplug() to trigger
cpu core unplug, which would call spapr_machine_device_unplug() ->
spapr_core_unplug() in the end.

This way unplug operation is not buried in spapr internals and located
in the same place like in other targets, following similar
logic/call chain across targets.

Acked-by: Igor Mammedov <address@hidden>
Acked-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d61c2857037e6211667a52563742af798d4c0332
      
https://github.com/qemu/qemu/commit/d61c2857037e6211667a52563742af798d4c0332
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/pnv_lpc.c
    M include/hw/ppc/pnv_lpc.h

  Log Message:
  -----------
  ppc/pnv: fix LPC HC firmware address space

A specific MemoryRegion is required for the LPC HC Firmware address
space.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bf358b541b803d8f415807a632c0d0cde1504bca
      
https://github.com/qemu/qemu/commit/bf358b541b803d8f415807a632c0d0cde1504bca
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/intc/xics_kvm.c

  Log Message:
  -----------
  xics_kvm: use KVM helpers

The KVM helpers hide the low level interface used to communicate to
the XICS KVM device and provide a good cleanup to the XICS KVM models.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 30f79dc13f116a79ff45d37ad0f5c035012064a7
      
https://github.com/qemu/qemu/commit/30f79dc13f116a79ff45d37ad0f5c035012064a7
  Author: David Gibson <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Remove unhelpful pagesize warning

By default, the IOMMU model built into the spapr virtual PCI host bridge
supports 4kiB and 64kiB IOMMU page sizes.  However this can be overridden
which may be desirable to allow larger IOMMU page sizes when running a
guest with hugepage backing and passthrough devices.  For that reason a
warning was printed when the device wasn't configured to allow the pagesize
with which guest RAM is backed.

Experience has proven, however, that this message is more confusing than
useful.  Worse it sometimes makes little sense when the host-available page
sizes don't match those available on the guest, which can happen with
a POWER8 guest running on a POWER9 KVM host.

Long term we do want better handling to allow large IOMMU page sizes to be
used, but for now this parameter and warning don't really accomplish it.
So, remove the message, pending a better solution.

Signed-off-by: David Gibson <address@hidden>


  Commit: 3b68de85b9b964e1bfb8474af1208717ba29b9ff
      
https://github.com/qemu/qemu/commit/3b68de85b9b964e1bfb8474af1208717ba29b9ff
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-12 (Tue, 12 Jun 2018)

  Changed paths:
    M MAINTAINERS
    M hw/i2c/ppc4xx_i2c.c
    M hw/intc/xics_kvm.c
    M hw/misc/macio/cuda.c
    M hw/misc/macio/macio.c
    M hw/misc/macio/trace-events
    M hw/misc/mos6522.c
    M hw/pci-host/uninorth.c
    M hw/ppc/mac.h
    M hw/ppc/pnv_lpc.c
    M hw/ppc/ppc440_pcix.c
    M hw/ppc/prep.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_drc.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/misc/macio/cuda.h
    M include/hw/misc/mos6522.h
    M include/hw/pci-host/uninorth.h
    M include/hw/ppc/pnv_lpc.h
    M include/hw/ppc/ppc.h
    M include/qemu/osdep.h
    M qemu-doc.texi
    M target/ppc/helper.h
    M target/ppc/kvm.c
    M target/ppc/misc_helper.c
    M target/ppc/translate.c
    M target/ppc/translate_init.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180612' into 
staging

ppc patch queue 2018-06-12

Here's another batch of ppc patches towards the 3.0 release.  There's
a fair bit here, because I've been working through my mail backlog
after a holiday.  There's not much of a central theme, amongst other
things we have:
    * ppc440 / sam460ex improvements
    * logging and error cleanups
    * 40p (PReP) bugfixes
    * Macintosh fixes and cleanups
    * Add emulation of the new POWER9 store-forwarding barrier
      instruction variant
    * Hotplug cleanups

# gpg: Signature made Tue 12 Jun 2018 07:43:21 BST
# gpg:                using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-3.0-20180612: (33 commits)
  spapr_pci: Remove unhelpful pagesize warning
  xics_kvm: use KVM helpers
  ppc/pnv: fix LPC HC firmware address space
  spapr: handle cpu core unplug via hotplug handler chain
  spapr: handle pc-dimm unplug via hotplug handler chain
  spapr: introduce machine unplug handler
  spapr: move memory hotplug support check into spapr_memory_pre_plug()
  spapr: move lookup of the node into spapr_memory_plug()
  spapr: no need to verify the node
  target/ppc: Allow PIR read in privileged mode
  ppc4xx_i2c: Clean up and improve error logging
  target/ppc: extend eieio for POWER9
  mos6522: convert VMSTATE_TIMER_PTR_TEST to VMSTATE_TIMER_PTR
  mos6522: move timer frequency initialisation to mos6522_reset
  cuda: embed mos6522_cuda device directly rather than using QOM object link
  mos6522: fix vmstate_mos6522_timer version in vmstate_mos6522
  ppc: add missing FW_CFG_PPC_NVRAM_FLAT definition
  ppc: remove obsolete macio_init() definition from mac.h
  ppc: remove obsolete pci_pmac_init() definitions from mac.h
  hw/misc/mos6522: Add trailing '\n' to qemu_log() calls
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/98d11a6e72c4...3b68de85b9b9
      **NOTE:** This service been marked for deprecation: 
https://developer.github.com/changes/2018-04-25-github-services-deprecation/

      Functionality will be removed from GitHub.com on January 31st, 2019.
[Prev in Thread]
Current Thread
[Next in Thread]
[Qemu-commits] [qemu/qemu] 681431: ppc440_pcix: Fix a typo in setting a register (Cov..., GitHub <=
Prev by Date: [Qemu-commits] [qemu/qemu] ab41fc: block: remove bdrv_dirty_bitmap_make_anon
Next by Date: [Qemu-commits] [qemu/qemu] 649ae1: usb: update docs
Previous by thread: [Qemu-commits] [qemu/qemu] ab41fc: block: remove bdrv_dirty_bitmap_make_anon
Next by thread: [Qemu-commits] [qemu/qemu] 649ae1: usb: update docs
Index(es):
- Date
- Thread