[Qemu-commits] [qemu/qemu] 2f2827: contrib: add a basic gitdm config

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2f28271d807edfcdc47a280c06999dd866dcae10
      
https://github.com/qemu/qemu/commit/2f28271d807edfcdc47a280c06999dd866dcae10
  Author: Alex Bennée <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    A contrib/gitdm/aliases
    A contrib/gitdm/domain-map
    A contrib/gitdm/filetypes.txt
    A contrib/gitdm/group-map-academics
    A contrib/gitdm/group-map-cadence
    A contrib/gitdm/group-map-codeweavers
    A contrib/gitdm/group-map-ibm
    A contrib/gitdm/group-map-individuals
    A contrib/gitdm/group-map-redhat
    A contrib/gitdm/group-map-wavecomp
    A gitdm.config

  Log Message:
  -----------
  contrib: add a basic gitdm config

This is a QEMU specific version of a gitdm config for generating
reports on the contributor base of the project. I've added enough
group maps and domain aliases to ensure the current top ten is as
reflective as it can be. As of this commit running:

  git log --numstat --since "Last Year" | gitdm -n -l 10

Reports:

  Top changeset contributors by employer
  Red Hat                   3172 (44.3%)
  Linaro                    1153 (16.1%)
  (None)                     549 (7.7%)
  IBM                        348 (4.9%)
  Academics (various)        170 (2.4%)
  Virtuozzo                  168 (2.3%)
  Wave Computing             118 (1.6%)
  Xilinx                     102 (1.4%)
  Igalia                      93 (1.3%)
  Cadence Design Systems      88 (1.2%)

  Top lines changed by employer
  Red Hat                   144092 (28.1%)
  Cadence Design Systems    126554 (24.6%)
  Linaro                    77480 (15.1%)
  Wave Computing            33134 (6.5%)
  SiFive                    14392 (2.8%)
  IBM                       12219 (2.4%)
  (None)                    11948 (2.3%)
  Academics (various)       10447 (2.0%)
  Virtuozzo                 10445 (2.0%)
  CodeWeavers               9179 (1.8%)

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Daniel P. Berrangé <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>


  Commit: 0636e4d899ab30485d18bacf286defff011a22c5
      
https://github.com/qemu/qemu/commit/0636e4d899ab30485d18bacf286defff011a22c5
  Author: Alex Bennée <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: update status of FPU emulation

Given I've spent a fair amount of time around this code now I'm
putting myself forward as a maintainer. Also given that the code has
been extensively re-written and has testing and new incoming features
it is probably more than just Odd Fixes.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>


  Commit: 6c49b06dfd1aa5c1f90b2ade10df5a305d348e08
      
https://github.com/qemu/qemu/commit/6c49b06dfd1aa5c1f90b2ade10df5a305d348e08
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M tests/fp/Makefile

  Log Message:
  -----------
  fp-test: pick TARGET_ARM to get its specialization

This gets rid of the muladd errors due to not raising the invalid flag.

- Before:
Errors found in f64_mulAdd, rounding near_even, tininess before rounding:
+000.0000000000000  +7FF.0000000000000  +7FF.FFFFFFFFFFFFF
  => +7FF.FFFFFFFFFFFFF .....  expected -7FF.FFFFFFFFFFFFF v....
[...]

- After:
In 6133248 tests, no errors found in f64_mulAdd, rounding near_even, tininess 
before rounding.
[...]

Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 588e6dfd8774e6da56b6995611655fbe59ff564a
      
https://github.com/qemu/qemu/commit/588e6dfd8774e6da56b6995611655fbe59ff564a
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: add float{32,64}_is_{de,}normal

This paves the way for upcoming work.

Reviewed-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: b8c547000dbaa403f524663e05ee2b1e69d3953f
      
https://github.com/qemu/qemu/commit/b8c547000dbaa403f524663e05ee2b1e69d3953f
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M target/tricore/fpu_helper.c

  Log Message:
  -----------
  target/tricore: use float32_is_denormal

Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: f9943c7f766678af36d31076b78e466256f4871b
      
https://github.com/qemu/qemu/commit/f9943c7f766678af36d31076b78e466256f4871b
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  softfloat: rename canonicalize to sf_canonicalize

glibc >= 2.25 defines canonicalize in commit eaf5ad0
(Add canonicalize, canonicalizef, canonicalizel., 2016-10-26).

Given that we'll be including <math.h> soon, prepare
for this by prefixing our canonicalize() with sf_ to avoid
clashing with the libc's canonicalize().

Reported-by: Bastian Koppelmann <address@hidden>
Tested-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 315df0d193929b167b9d7be4665d5f2c0e2427e0
      
https://github.com/qemu/qemu/commit/315df0d193929b167b9d7be4665d5f2c0e2427e0
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M include/fpu/softfloat.h

  Log Message:
  -----------
  softfloat: add float{32,64}_is_zero_or_normal

These will gain some users very soon.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 25f539f359447cd0dbfd5954aaa3c22b3921af79
      
https://github.com/qemu/qemu/commit/25f539f359447cd0dbfd5954aaa3c22b3921af79
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M tests/fp/.gitignore
    M tests/fp/Makefile
    A tests/fp/fp-bench.c

  Log Message:
  -----------
  tests/fp: add fp-bench

These microbenchmarks will allow us to measure the performance impact of
FP emulation optimizations. Note that we can measure both directly the impact
on the softfloat functions (with "-t soft"), or the impact on an
emulated workload (call with "-t host" and run under qemu user-mode).

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: a94b783952cc493cb241aabb1da8c7a830385baa
      
https://github.com/qemu/qemu/commit/a94b783952cc493cb241aabb1da8c7a830385baa
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  fpu: introduce hardfloat

The appended paves the way for leveraging the host FPU for a subset
of guest FP operations. For most guest workloads (e.g. FP flags
aren't ever cleared, inexact occurs often and rounding is set to the
default [to nearest]) this will yield sizable performance speedups.

The approach followed here avoids checking the FP exception flags register.
See the added comment for details.

This assumes that QEMU is running on an IEEE754-compliant FPU and
that the rounding is set to the default (to nearest). The
implementation-dependent specifics of the FPU should not matter; things
like tininess detection and snan representation are still dealt with in
soft-fp. However, this approach will break on most hosts if we compile
QEMU with flags that break IEEE compatibility. There is no way to detect
all of these flags at compilation time, but at least we check for
-ffast-math (which defines __FAST_MATH__) and disable hardfloat
(plus emit a #warning) when it is set.

This patch just adds common code. Some operations will be migrated
to hardfloat in subsequent patches to ease bisection.

Note: some architectures (at least PPC, there might be others) clear
the status flags passed to softfloat before most FP operations. This
precludes the use of hardfloat, so to avoid introducing a performance
regression for those targets, we add a flag to disable hardfloat.
In the long run though it would be good to fix the targets so that
at least the inexact flag passed to softfloat is indeed sticky.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 1b615d482094e0123d187f0ad3c676ba8eb9d0a3
      
https://github.com/qemu/qemu/commit/1b615d482094e0123d187f0ad3c676ba8eb9d0a3
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 addition and subtraction

Performance results (single and double precision) for fp-bench:

1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
add-single: 135.07 MFlops
add-double: 131.60 MFlops
sub-single: 130.04 MFlops
sub-double: 133.01 MFlops
- after:
add-single: 443.04 MFlops
add-double: 301.95 MFlops
sub-single: 411.36 MFlops
sub-double: 293.15 MFlops

2. ARM Aarch64 A57 @ 2.4GHz
- before:
add-single: 44.79 MFlops
add-double: 49.20 MFlops
sub-single: 44.55 MFlops
sub-double: 49.06 MFlops
- after:
add-single: 93.28 MFlops
add-double: 88.27 MFlops
sub-single: 91.47 MFlops
sub-double: 88.27 MFlops

3. IBM POWER8E @ 2.1 GHz
- before:
add-single: 72.59 MFlops
add-double: 72.27 MFlops
sub-single: 75.33 MFlops
sub-double: 70.54 MFlops
- after:
add-single: 112.95 MFlops
add-double: 201.11 MFlops
sub-single: 116.80 MFlops
sub-double: 188.72 MFlops

Note that the IBM and ARM machines benefit from having
HARDFLOAT_2F{32,64}_USE_FP set to 0. Otherwise their performance
can suffer significantly:
- IBM Power8:
add-single: [1] 54.94 vs [0] 116.37 MFlops
add-double: [1] 58.92 vs [0] 201.44 MFlops
- Aarch64 A57:
add-single: [1] 80.72 vs [0] 93.24 MFlops
add-double: [1] 82.10 vs [0] 88.18 MFlops

On the Intel machine, having 2F64 set to 1 pays off, but it
doesn't for 2F32:
- Intel i7-6700K:
add-single: [1] 285.79 vs [0] 426.70 MFlops
add-double: [1] 302.15 vs [0] 278.82 MFlops

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 2dfabc86e656e835c67954c60e143ecd33e15817
      
https://github.com/qemu/qemu/commit/2dfabc86e656e835c67954c60e143ecd33e15817
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 multiplication

Performance results for fp-bench:

1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
mul-single: 126.91 MFlops
mul-double: 118.28 MFlops
- after:
mul-single: 258.02 MFlops
mul-double: 197.96 MFlops

2. ARM Aarch64 A57 @ 2.4GHz
- before:
mul-single: 37.42 MFlops
mul-double: 38.77 MFlops
- after:
mul-single: 73.41 MFlops
mul-double: 76.93 MFlops

3. IBM POWER8E @ 2.1 GHz
- before:
mul-single: 58.40 MFlops
mul-double: 59.33 MFlops
- after:
mul-single: 60.25 MFlops
mul-double: 94.79 MFlops

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: 4a6295613f533a6841de5968c50e1ca36748807e
      
https://github.com/qemu/qemu/commit/4a6295613f533a6841de5968c50e1ca36748807e
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 division

Performance results for fp-bench:

1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
div-single: 34.84 MFlops
div-double: 34.04 MFlops
- after:
div-single: 275.23 MFlops
div-double: 216.38 MFlops

2. ARM Aarch64 A57 @ 2.4GHz
- before:
div-single: 9.33 MFlops
div-double: 9.30 MFlops
- after:
div-single: 51.55 MFlops
div-double: 15.09 MFlops

3. IBM POWER8E @ 2.1 GHz
- before:
div-single: 25.65 MFlops
div-double: 24.91 MFlops
- after:
div-single: 96.83 MFlops
div-double: 31.01 MFlops

Here setting 2FP64_USE_FP to 1 pays off for x86_64:
[1] 215.97 vs [0] 62.15 MFlops

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: ccf770ba7396c240ca8a1564740083742dd04c08
      
https://github.com/qemu/qemu/commit/ccf770ba7396c240ca8a1564740083742dd04c08
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 fused multiply-add

Performance results for fp-bench:

1. Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
fma-single: 74.73 MFlops
fma-double: 74.54 MFlops
- after:
fma-single: 203.37 MFlops
fma-double: 169.37 MFlops

2. ARM Aarch64 A57 @ 2.4GHz
- before:
fma-single: 23.24 MFlops
fma-double: 23.70 MFlops
- after:
fma-single: 66.14 MFlops
fma-double: 63.10 MFlops

3. IBM POWER8E @ 2.1 GHz
- before:
fma-single: 37.26 MFlops
fma-double: 37.29 MFlops
- after:
fma-single: 48.90 MFlops
fma-double: 59.51 MFlops

Here having 3FP64 set to 1 pays off for x86_64:
[1] 170.15 vs [0] 153.12 MFlops

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: f131bae8a7b7ed1928cc94c69df291db609c316a
      
https://github.com/qemu/qemu/commit/f131bae8a7b7ed1928cc94c69df291db609c316a
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 square root

Performance results for fp-bench:

Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
sqrt-single: 42.30 MFlops
sqrt-double: 22.97 MFlops
- after:
sqrt-single: 311.42 MFlops
sqrt-double: 311.08 MFlops

Here USE_FP makes a huge difference for f64's, with throughput
going from ~200 MFlops to ~300 MFlops.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: d9fe9db943d4e855a75424978d7ab87fd54edd98
      
https://github.com/qemu/qemu/commit/d9fe9db943d4e855a75424978d7ab87fd54edd98
  Author: Emilio G. Cota <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  hardfloat: implement float32/64 comparison

Performance results for fp-bench:

Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
- before:
cmp-single: 110.98 MFlops
cmp-double: 107.12 MFlops
- after:
cmp-single: 506.28 MFlops
cmp-double: 524.77 MFlops

Note that flattening both eq and eq_signaling versions
would give us extra performance (695v506, 615v524 Mflops
for single/double, respectively) but this would emit two
essentially identical functions for each eq/signaling pair,
which is a waste.

Aggregate performance improvement for the last few patches:
[ all charts in png: https://imgur.com/a/4yV8p ]

1. Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
              qemu-aarch64 NBench score; higher is better
           Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz

  16 +-+-----------+-------------+----===-------+---===-------+-----------+-+
  14 +-+..........................@@@&&.=.......@@@&&.=...................+-+
  12 address@hidden@.&address@hidden@.&.=.....+befor===     +-+
  10 address@hidden@.&address@hidden@.&.=.....+ad@@&& =     +-+
   8 address@hidden&address@hidden@.&.=.....+  @@u& =     +-+
   6 +-+............@@@&&address@hidden&address@hidden&address@hidden& =     +-+
   4 address@hidden&address@hidden&address@hidden&.=+**.#+$ address@hidden& =   
  +-+
   2 address@hidden&address@hidden&address@hidden&.=.**.#+$+sqr& =     +-+
   0 +-+-----***##$%%@@&&=-***##$$%@@&&==***##$$%@@&&==-**##$$%+cmp==-----+-+
      FOURIER    NEURAL NELU DECOMPOSITION         gmean
                         qemu-aarch64 SPEC06fp (test set) speedup over QEMU 
4c2c1015905
                                Host: Intel(R) Core(TM) i7-6700K CPU @ 4.00GHz
                                      error bars: 95% confidence interval

  4.5 
+-+---+-----+----+-----+-----+-&---+-----+----+-----+-----+-----+----+-----+-----+-----+-----+----+-----+---+-+
    4 
+-+..........................+@@+...........................................................................+-+
  3.5 
+-+..............%%@&.........@@..............%%@&............................................+++dsub
       +-+
  2.5 
+-+....&&+.......%%@&address@hidden&+..@@&+.%%@&....................................+%%&+.+%@&++%%@&
      +-+
    2 
+-+..+%%&..+%@&+.%%@&address@hidden&.+$$@&..%%@&..%%@&.......+%%&+.%%@&+......+%%@&.+%%&++$$@&++d%@&
  %%@&+-+
  1.5 
+-+**#$%&**#$@&**#%@&address@hidden@**#$%&**#$@&**$%@&address@hidden@**#$%&**#%@&**$%@&address@hidden&**#$@&*+f%@&**$%@&+-+
  0.5 
+-+**#$%&**#$@&**#%@&address@hidden@**#$%&**#$@&**$%@&address@hidden@**#$%&**#%@&**$%@&address@hidden&**#$@&+sqr@&**$%@&+-+
    0 
+-+**#$%&**#$@&**#%@&address@hidden@**#$%&**#$@&**$%@&address@hidden@**#$%&**#%@&**$%@&address@hidden&**#$@&*+cmp&**$%@&+-+
  
410.bw416.gam433.434.z435.436.cac437.lesli444.447.de450.so453454.ca459.GemsF465.tont470.lb4482.sphinxgeomean

2. Host: ARM Aarch64 A57 @ 2.4GHz
               qemu-aarch64 NBench score; higher is better
           Host: Applied Micro X-Gene, Aarch64 A57 @ 2.4 GHz

    5 +-+-----------+-------------+-------------+-------------+-----------+-+
  4.5 +-+........................................@@@&==...................+-+
  3 4 +-+..........................@@@&address@hidden@&.=.....+before       +-+
    3 address@hidden@&address@hidden@&.=.....+ad@@@&==     +-+
  2.5 +-+.....................##$$%%.@&address@hidden@&.=.....+  @m@& =     +-+
    2 +-+............@@@&==.***#.$.%.@&.=.***#$$%%.@&.=.***#$$%%d@& =     +-+
  1.5 +-+.....***#$$%%.@&.=.*.*#.$.%.@&.=.*.*#.$.%.@&.=.*.*#+$ +f@& =     +-+
  0.5 +-+.....*.*#.$.%.@&.=.*.*#.$.%.@&.=.*.*#.$.%.@&.=.*.*#+$+sqr& =     +-+
    0 +-+-----***#$$%%@@&==-***#$$%%@@&==-***#$$%%@@&==-***#$$%+cmp==-----+-+
       FOURIER    NEURAL NLU DECOMPOSITION         gmean

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>


  Commit: ec3c927f3d983b277d00fb88e26785c94e545af3
      
https://github.com/qemu/qemu/commit/ec3c927f3d983b277d00fb88e26785c94e545af3
  Author: Peter Maydell <address@hidden>
  Date:   2018-12-17 (Mon, 17 Dec 2018)

  Changed paths:
    M MAINTAINERS
    A contrib/gitdm/aliases
    A contrib/gitdm/domain-map
    A contrib/gitdm/filetypes.txt
    A contrib/gitdm/group-map-academics
    A contrib/gitdm/group-map-cadence
    A contrib/gitdm/group-map-codeweavers
    A contrib/gitdm/group-map-ibm
    A contrib/gitdm/group-map-individuals
    A contrib/gitdm/group-map-redhat
    A contrib/gitdm/group-map-wavecomp
    M fpu/softfloat.c
    A gitdm.config
    M include/fpu/softfloat.h
    M target/tricore/fpu_helper.c
    M tests/fp/.gitignore
    M tests/fp/Makefile
    A tests/fp/fp-bench.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/stsquad/tags/pull-hardfloat-and-gitdm-171218-3' into staging

Hardfloat + maintainers and gitdm

# gpg: Signature made Mon 17 Dec 2018 10:55:19 GMT
# gpg:                using RSA key FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <address@hidden>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-hardfloat-and-gitdm-171218-3:
  hardfloat: implement float32/64 comparison
  hardfloat: implement float32/64 square root
  hardfloat: implement float32/64 fused multiply-add
  hardfloat: implement float32/64 division
  hardfloat: implement float32/64 multiplication
  hardfloat: implement float32/64 addition and subtraction
  fpu: introduce hardfloat
  tests/fp: add fp-bench
  softfloat: add float{32,64}_is_zero_or_normal
  softfloat: rename canonicalize to sf_canonicalize
  target/tricore: use float32_is_denormal
  softfloat: add float{32,64}_is_{de,}normal
  fp-test: pick TARGET_ARM to get its specialization
  MAINTAINERS: update status of FPU emulation
  contrib: add a basic gitdm config

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f163448536e5...ec3c927f3d98
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