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[Qemu-commits] [qemu/qemu] 6230da: target/xtensa: add qemu_cpu_kick to x


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 6230da: target/xtensa: add qemu_cpu_kick to xtensa_runstall
Date: Tue, 05 Feb 2019 02:59:13 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6230dac89b19d50567c44434b37a4c48a84ec200
      
https://github.com/qemu/qemu/commit/6230dac89b19d50567c44434b37a4c48a84ec200
  Author: Max Filippov <address@hidden>
  Date:   2019-01-24 (Thu, 24 Jan 2019)

  Changed paths:
    M target/xtensa/helper.c

  Log Message:
  -----------
  target/xtensa: add qemu_cpu_kick to xtensa_runstall

When xtensa_runstall is called to unstall a core it needs to kick it
after clearing runstall flag, otherwise the core doesn't start
immediately. There's also no point in clearing CPU_INTERRUPT_HALT, drop
it.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 288a3f2ed70400bcb6fbabbe30410ee58f8263ba
      
https://github.com/qemu/qemu/commit/288a3f2ed70400bcb6fbabbe30410ee58f8263ba
  Author: Max Filippov <address@hidden>
  Date:   2019-01-24 (Thu, 24 Jan 2019)

  Changed paths:
    M hw/xtensa/xtfpga.c

  Log Message:
  -----------
  hw/xtensa: xtfpga: fix bootloader placement in SMP

Use BSP reset PC as a place for the mini-bootloader because in SMP
configurations APs and BSP may have different boot addresses.
This fixes SMP linux uImage boot on xtfpga boards.

Signed-off-by: Max Filippov <address@hidden>


  Commit: fff7bf145045ec57be6bd3bdd69de7930137654c
      
https://github.com/qemu/qemu/commit/fff7bf145045ec57be6bd3bdd69de7930137654c
  Author: Max Filippov <address@hidden>
  Date:   2019-01-24 (Thu, 24 Jan 2019)

  Changed paths:
    M hw/xtensa/xtfpga.c

  Log Message:
  -----------
  hw/xtensa: xtfpga: use core frequency

XTFPGA board FPGA peripheral exposes hard-coded 10MHz frequency
regardless of the actual used core frequency. Expose actual core
frequency instead.

Signed-off-by: Max Filippov <address@hidden>


  Commit: fa92bd4af71bed76bf57bb1c8b5465414a52ab3f
      
https://github.com/qemu/qemu/commit/fa92bd4af71bed76bf57bb1c8b5465414a52ab3f
  Author: Max Filippov <address@hidden>
  Date:   2019-01-24 (Thu, 24 Jan 2019)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/exc_helper.c
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: fix access to the INTERRUPT SR

INTERRUPT special register may be changed both by the core (by writing
to INTSET and INTCLEAR registers) and by external events (by triggering
and clearing HW IRQs). In MTTCG this state must be protected from
concurrent access, otherwise interrupts may be lost or spurious
interrupts may be detected.

Use atomic operations to change INTSET SR.
Fix wsr.intset so that it soesn't clear any bits.
Fix wsr.intclear so that it doesn't clear bit that corresponds to NMI.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 3f75038a3369078b656826eb454ead5f5dc8802e
      
https://github.com/qemu/qemu/commit/3f75038a3369078b656826eb454ead5f5dc8802e
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/cpu.h

  Log Message:
  -----------
  target/xtensa: drop function xtensa_timer_irq

It's a one-liner used in a single place, move its implementation there
and remove its declaration.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Max Filippov <address@hidden>


  Commit: 66f03d7e13d2abe56c6b1841faf0edf5b4ec4b66
      
https://github.com/qemu/qemu/commit/66f03d7e13d2abe56c6b1841faf0edf5b4ec4b66
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M hw/xtensa/xtfpga.c
    M target/xtensa/cpu.h

  Log Message:
  -----------
  target/xtensa: rearrange access to external interrupts

Replace xtensa_get_extint that returns single external IRQ descriptor
with xtensa_get_extints that returns a vector of all external IRQs.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Max Filippov <address@hidden>


  Commit: 17a86b0e9f64c00f3e438d903d3fa475255630cf
      
https://github.com/qemu/qemu/commit/17a86b0e9f64c00f3e438d903d3fa475255630cf
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/pic_cpu.c
    M target/xtensa/cpu.h

  Log Message:
  -----------
  target/xtensa: expose core runstall as an IRQ line

Runstall signal looks very much like a level-triggered IRQ line. Provide
xtensa_get_runstall function that returns runstall IRQ.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 10df8ff146ff0219cf746ac13ffa870c4cf0350a
      
https://github.com/qemu/qemu/commit/10df8ff146ff0219cf746ac13ffa870c4cf0350a
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/Makefile.objs
    A hw/xtensa/mx_pic.c
    A include/hw/xtensa/mx_pic.h

  Log Message:
  -----------
  target/xtensa: add MX interrupt controller

MX interrupt controller is a collection of the following devices
accessible through the external registers interface:
- interrupt distributor can route each external IRQ line to the
  corresponding external IRQ pin of selected subset of connected xtensa
  cores. It has per-CPU and per-IRQ enable signals and per-IRQ software
  assert signals;
- IPI controller has 16 per-CPU IPI signals that may be routed to a
  combination of 3 designated external IRQ pins of connected xtensa
  cores;
- cache coherecy register controls core L1 cache participation in the
  SMP cluster cache coherency protocol;
- runstall register lets BSP core stall and unstall AP cores.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 1acd90bff27eb1f060a7243acb771f444e61d205
      
https://github.com/qemu/qemu/commit/1acd90bff27eb1f060a7243acb771f444e61d205
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/xtfpga.c

  Log Message:
  -----------
  hw/xtensa: xtfpga: use MX PIC for SMP

Create and use MX PIC as a peripheral interrupt controller when more
than 1 processor is enabled on xtfpga board. Connect xtensa CPU cores to
the MX PIC and select secondary reset vector on all cores except the
first one.

Signed-off-by: Max Filippov <address@hidden>


  Commit: d848ea77672851f3f385280fec66ef9f03a25f7e
      
https://github.com/qemu/qemu/commit/d848ea77672851f3f385280fec66ef9f03a25f7e
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M target/xtensa/Makefile.objs
    A target/xtensa/core-test_mmuhifi_c3.c
    A target/xtensa/core-test_mmuhifi_c3/core-isa.h
    A target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
    A target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c

  Log Message:
  -----------
  target/xtensa: add test_mmuhifi_c3 core

test_mmuhifi_c3 is an MMUv2 SMP-capable xtensa core.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 174e09b73ab1c47408dd29fb36c4dd9fbda54f97
      
https://github.com/qemu/qemu/commit/174e09b73ab1c47408dd29fb36c4dd9fbda54f97
  Author: Max Filippov <address@hidden>
  Date:   2019-01-28 (Mon, 28 Jan 2019)

  Changed paths:
    M hw/xtensa/xtfpga.c

  Log Message:
  -----------
  hw/xtensa: xtfpga: raise CPU number limit

MX PIC can support up to 32 CPUs on xtfpga boards, raise per-board
limit accordingly.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 9ae805637a9cfab2edc15f56fbc3219815c8118e
      
https://github.com/qemu/qemu/commit/9ae805637a9cfab2edc15f56fbc3219815c8118e
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-05 (Tue, 05 Feb 2019)

  Changed paths:
    M hw/xtensa/Makefile.objs
    A hw/xtensa/mx_pic.c
    M hw/xtensa/pic_cpu.c
    M hw/xtensa/xtfpga.c
    A include/hw/xtensa/mx_pic.h
    M target/xtensa/Makefile.objs
    A target/xtensa/core-test_mmuhifi_c3.c
    A target/xtensa/core-test_mmuhifi_c3/core-isa.h
    A target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
    A target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
    M target/xtensa/cpu.h
    M target/xtensa/exc_helper.c
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/xtensa/tags/20190204-xtensa' into 
staging

target/xtensa: SMP updates and various fixes

- fix CPU wakeup on runstall changes; expose runstall as an IRQ line;
- place mini-bootloader at the BSP reset vector;
- expose CPU core frequency in XTFPGA board FPGA register;
- rearrange access to external interrupts of xtensa cores;
- add MX interrupt distributor and use it on SMP XTFPGA boards;
- add test_mmuhifi_c3 xtensa core variant;
- raise number of CPUs that can be instantiated on XTFPGA boards.

# gpg: Signature made Mon 04 Feb 2019 18:59:32 GMT
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Max Filippov <address@hidden>" [unknown]
# gpg:                 aka "Max Filippov <address@hidden>" [full]
# gpg:                 aka "Max Filippov <address@hidden>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20190204-xtensa:
  hw/xtensa: xtfpga: raise CPU number limit
  target/xtensa: add test_mmuhifi_c3 core
  hw/xtensa: xtfpga: use MX PIC for SMP
  target/xtensa: add MX interrupt controller
  target/xtensa: expose core runstall as an IRQ line
  target/xtensa: rearrange access to external interrupts
  target/xtensa: drop function xtensa_timer_irq
  target/xtensa: fix access to the INTERRUPT SR
  hw/xtensa: xtfpga: use core frequency
  hw/xtensa: xtfpga: fix bootloader placement in SMP
  target/xtensa: add qemu_cpu_kick to xtensa_runstall

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/773c4a6228fd...9ae805637a9c



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