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Re: [Qemu-devel] ARM load/store multiple bug

From: Justin Fletcher
Subject: Re: [Qemu-devel] ARM load/store multiple bug
Date: Sun, 10 Sep 2006 11:43:07 +0100 (BST)

On Sun, 10 Sep 2006, Paul Brook wrote:

                         if (n != 1)
                             gen_op_addl_T1_im(-((n - 1) * 4));
                 j = 0;
/* Insert something like gen_op_bicl_T1_im(3); here */
                 for(i=0;i<16;i++) {
                     if (insn & (1 << i)) {
                         if (insn & (1 << 20)) {

This is not sufficient. It breaks base register writeback.

Doh! Of course, yes.

I'll also note that the behavior is dependent on alignment traps being
disabled (and unaligned access on some cores). ie. for linux user mode
emulation the current behavior is acceptable.

Fair enough; it fails badly on some of the code in the OS I'm running on it. With a bit of looking around I decided the easiest way to do the operation and maintain the compatibility with the writeback was to introduce a pair of new operations for load and store, forced to aligned addresses. This is NOT, as you note, ideal because it moves the problem of the alignment checks and should probably be done better - I don't know the code well enough, I'm afraid, to know the right or best way to do it.

My solution is to add new operations to target-arm/op_mem.h :

/* Load from aligned address T1 into T0 (used for LDM) */
#define MEM_LDA_OP(name) \
void OPPROTO glue(op_lda##name,MEMSUFFIX)(void) \
{ \
    /* JRF: Note should raise alignment fault if alignment in use and \
            b0 or b1 set */ \
    T0 = glue(ld##name,MEMSUFFIX)(T1 &~3); \
    FORCE_RET(); \

#undef MEM_LDA_OP

/* Store aligned address T0 into T1 (used for STM) */
#define MEM_STA_OP(name) \
void OPPROTO glue(op_sta##name,MEMSUFFIX)(void) \
{ \
    /* JRF: Note should raise alignment fault if alignment in use and \
            b0 or b1 set */ \
    glue(st##name,MEMSUFFIX)(T1 &~3, T0); \
    FORCE_RET(); \

#undef MEM_STA_OP

And to replace the load and store operations in the LDM/STM implementation in target-arm/translate.c to use these, eg :

       if (insn & (1 << 20)) {
         /* load */
         gen_ldst(ldal, s); /* JRF: was ldl */
         if (i == 15)

and :

           gen_movl_T0_reg(s, i);
         gen_ldst(stal, s); /* JRF: was stl */

I realise that these are not good for the generic use, but they solve my problems and it may solve other people's if they happen to be using a similarly constructed OS.

Gerph <http://gerph.org/>
... Hand to mouth, we're picking up the thread

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