Hi,
The patch below implements the cvt.s.d and cvt.d.s instructions for the
mips target. They are need to be able to execute the cp and the find
programs.
Bye,
Aurelien
Index: target-mips/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/op.c,v
retrieving revision 1.9
diff -u -r1.9 op.c
--- target-mips/op.c 26 Jun 2006 20:29:47 -0000 1.9
+++ target-mips/op.c 28 Sep 2006 23:42:30 -0000
@@ -785,12 +785,24 @@
#define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void)
+FLOAT_OP(cvtd, s)
+{
+ FDT2 = float32_to_float64(WT0, &env->fp_status);
+ DEBUG_FPU_STATE();
+ RETURN();
+}
FLOAT_OP(cvtd, w)
{
FDT2 = int32_to_float64(WT0, &env->fp_status);
DEBUG_FPU_STATE();
RETURN();
}
+FLOAT_OP(cvts, d)
+{
+ FST2 = float64_to_float32(WT0, &env->fp_status);
+ DEBUG_FPU_STATE();
+ RETURN();
+}
FLOAT_OP(cvts, w)
{
FST2 = int32_to_float32(WT0, &env->fp_status);
Index: target-mips/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate.c,v
retrieving revision 1.15
diff -u -r1.15 translate.c
--- target-mips/translate.c 26 Jun 2006 20:02:45 -0000 1.15
+++ target-mips/translate.c 28 Sep 2006 23:42:30 -0000
@@ -1675,6 +1675,13 @@
GEN_STORE_FTN_FREG(fd, WT2);
opn = "ceil.w.d";
break;
+ case FOP(33, 16): /* cvt.d.s */
+ CHECK_FR(ctx, fs | fd);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_cvtd_s();
+ GEN_STORE_FTN_FREG(fd, DT2);
+ opn = "cvt.d.s";
+ break;
case FOP(33, 20): /* cvt.d.w */
CHECK_FR(ctx, fs | fd);
GEN_LOAD_FREG_FTN(WT0, fs);
@@ -1782,6 +1789,13 @@
GEN_STORE_FTN_FREG(fd, WT2);
opn = "trunc.w.s";
break;
+ case FOP(32, 17): /* cvt.s.d */
+ CHECK_FR(ctx, fs | fd);
+ GEN_LOAD_FREG_FTN(WT0, fs);
+ gen_op_float_cvts_d();
+ GEN_STORE_FTN_FREG(fd, WT2);
+ opn = "cvt.s.d";
+ break;
case FOP(32, 20): /* cvt.s.w */
CHECK_FR(ctx, fs | fd);
GEN_LOAD_FREG_FTN(WT0, fs);