Re: [Qemu-devel] [PATCH] Huge TLB performance improvement

[Daniel Jacobowitz]

On Sun, Nov 12, 2006 at 10:07:15AM -0500, Daniel Jacobowitz wrote:
> > Actually that gives me an idea. When a TLB entry with a different ASID gets 
> > evicted we currently flush that page. This should be a no-op because we 
> > already did a full flush when the ASID changed.
> 
> Let me see if this makes any difference.

Saves about 2% of invalidate_tlb calls, no measurable time change, but
we might as well.  Attached.

-- 
Daniel Jacobowitz
CodeSourcery

---
 target-mips/op_helper.c |    7 +++++++
 1 file changed, 7 insertions(+)

Index: qemu/target-mips/op_helper.c
===================================================================
--- qemu.orig/target-mips/op_helper.c   2006-11-12 10:09:44.000000000 -0500
+++ qemu/target-mips/op_helper.c        2006-11-12 10:21:16.000000000 -0500
@@ -573,8 +573,15 @@ static void invalidate_tlb (int idx)
 {
     tlb_t *tlb;
     target_ulong addr;
+    uint8_t ASID;
+
+    ASID = env->CP0_EntryHi & 0xFF;
 
     tlb = &env->tlb[idx];
+    if (tlb->G == 0 && tlb->ASID != ASID) {
+        return;
+    }
+
     if (tlb->V0) {
         tb_invalidate_page_range(tlb->PFN[0], tlb->end - tlb->VPN);
         addr = tlb->VPN;