[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] qemu on mips patch

From: Jun Peng
Subject: Re: [Qemu-devel] qemu on mips patch
Date: Thu, 7 Jun 2007 16:05:37 +0800

2007/6/3, Thiemo Seufer <address@hidden>:
> ... I think the current
> CVS version does the right thing without relying on on an equivalent
> to your op_mips.c tool.
> ...

On my computer, I do not think so.

in op.o, -fno-PIC -mno-abicalls
004eb0d4 <op_divb_AL_T0>:
  4eb104: afa50010 sw a1,16(sp)
  4eb108: 14600003 bnez v1,4eb118 <op_divb_AL_T0+0x44>
  4eb10c: 00000000 nop
  4eb110: 0c140e12 jal 503848 <raise_exception>
  4eb114: 00000000 nop
  4eb118: 8fa30010 lw v1,16(sp)
  4eb11c: 00002021 move a0,zero

in helper.o, PIC and abicalls
00503848 <raise_exception>:
  503848: 3c1c000c lui gp,0xc
  50384c: 279c0858 addiu gp,gp,2136
  503850: 0399e021 addu gp,gp,t9
  503854: 8f998db8 lw t9,-29256(gp)
  503858: 00002821 move a1,zero
  50385c: 00003021 move a2,zero
  503860: 03200008 jr t9
  503864: 00003821 move a3,zero

When op_divb_AL_T0() calls raise_exception(), $t9 is not address of raise_exception().

in op.h
case INDEX_op_divb_AL_T0: {
    /* R_MIPS_26 RELOC, offset 0x10d0, name raise_exception */
    *(uint32_t *)(gen_code_ptr + 0x3c) = (0xc000000 & ~0x3fffff) | ((0xc000000 + (((long)(&raise_exception) - (*(uint32_t *)(gen_code_ptr + 0x3c))) >> 2))    & 0x3fffff);

jal(R_MIPS_26) is a PC-region branch, not PC-relative.

reply via email to

[Prev in Thread] Current Thread [Next in Thread]