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Re: [Qemu-devel] [PATCH, RFC] More than 2G of memory on 64-bit hosts

From: Gwenole Beauchesne
Subject: Re: [Qemu-devel] [PATCH, RFC] More than 2G of memory on 64-bit hosts
Date: Fri, 29 Jun 2007 16:26:10 +0200


2007/6/26, Karl Magdsick <address@hidden>:

With proper support from the compiler, it's theoretically possible on
x86-64 systems to use 32-bit pointers in long mode (16 general purpose
64-bit registers).  (There's an instruction prefix that will cause the
CPU to perform 32-bit pointer calculations in the 64-bit address
space.) I'm not aware of any systems that use this, however.

IIRC, there used to be an ILP32 programming model in long mode for
older AMD64 prototypes, i.e. with access to full 64-bit registers.
However, nobody was interested in it at that time so this was dropped.

There is still however, as you mention, an override prefix to do
32-bit pointer calculation (0x67). Please note documents around the
Intel Core processor mention a 5 cycle penalty when you use this
prefix. This doesn't seem to be a penalty for AMD processors though.
In practise, the impact on the generated code performance of my JIT
was measurably marginal (well, I only tested against my Core 2 and
Athlon 64 CPUs).

BTW, before I switched to using the address override prefix, I used to
implement a so-called 33-bit addressing mode in BasiliskII. That is,
the emulated address space is doubled to cope with the excess bits
during calculation. A shared segment is shm_open()'ed and then
mmap()'ed to BASE and BASE+(1L<<32).

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