[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code suppo
Re: [Qemu-devel] [PATCH, RFC] Disable implicit self-modifying code support for RISC CPUs
Sat, 3 Nov 2007 20:37:07 +0000
Blue Swirl wrote:
> RISC CPUs don't support self-modifying code unless the affected area
> is flushed explicitly.
Not entirely true. There are cacheless MIPS CPUs (the m4k), and also
cache-snooping MIPS CPUs (the R1x000).
> This patch disables the extra effort for SMC.
> The changes in this version would affect all CPUs except x86, but I'd
> like to see if there are problems with some target, so that the
> committed change can be limited. Without comments, I'll just disable
> SMC for Sparc, as there are no problems. So please comment, especially
> if you want to "opt in".
I prefer at least MIPS to stay as is.