[Qemu-devel] [PATCH] sparc32: add ecc irq

[Robert Reif]

Index: hw/eccmemctl.c
===================================================================
RCS file: /sources/qemu/qemu/hw/eccmemctl.c,v
retrieving revision 1.2
diff -p -u -r1.2 eccmemctl.c
--- hw/eccmemctl.c      1 Jan 2008 17:06:38 -0000       1.2
+++ hw/eccmemctl.c      6 Jan 2008 15:03:52 -0000
@@ -68,7 +68,7 @@
 #define ECC_FAR0_TYPE  0x000000f0      /* Transaction type */
 #define ECC_FAR0_SIZE  0x00000700      /* Transaction size */
 #define ECC_FAR0_CACHE 0x00000800      /* Mapped cacheable */
-#define ECC_FAR0_LOCK  0x00001000      /* Error occurred in attomic cycle */
+#define ECC_FAR0_LOCK  0x00001000      /* Error occurred in atomic cycle */
 #define ECC_FAR0_BMODE 0x00002000      /* Boot mode */
 #define ECC_FAR0_VADDR 0x003fc000      /* VA[12-19] (superset bits) */
 #define ECC_FAR0_S     0x08000000      /* Supervisor mode */
@@ -90,6 +90,7 @@
 #define ECC_ADDR_MASK  (ECC_SIZE - 1)
 
 typedef struct ECCState {
+    qemu_irq irq;
     uint32_t regs[ECC_NREGS];
 } ECCState;
 
@@ -222,7 +223,7 @@ static void ecc_reset(void *opaque)
         s->regs[i] = 0;
 }
 
-void * ecc_init(target_phys_addr_t base, uint32_t version)
+void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
 {
     int ecc_io_memory;
     ECCState *s;
@@ -232,6 +233,7 @@ void * ecc_init(target_phys_addr_t base,
         return NULL;
 
     s->regs[0] = version;
+    s->irq = irq;
 
     ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
     cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
Index: hw/sun4m.c
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.c,v
retrieving revision 1.80
diff -p -u -r1.80 sun4m.c
--- hw/sun4m.c  6 Jan 2008 07:50:38 -0000       1.80
+++ hw/sun4m.c  6 Jan 2008 15:03:52 -0000
@@ -91,7 +91,7 @@ struct hwdef {
     // IRQ numbers are not PIL ones, but master interrupt controller
     // register bit numbers
     int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
-    int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
+    int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
     int machine_id; // For NVRAM
     uint32_t iommu_version;
     uint32_t intbit_to_level[32];
@@ -528,7 +528,8 @@ static void sun4m_hw_init(const struct h
                graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
 
     if (hwdef->ecc_base != (target_phys_addr_t)-1)
-        ecc_init(hwdef->ecc_base, hwdef->ecc_version);
+        ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
+                 hwdef->ecc_version);
 }
 
 static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
@@ -742,6 +743,7 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
+        .ecc_irq = 28,
         .machine_id = 0x72,
         .iommu_version = 0x03000000,
         .intbit_to_level = {
@@ -783,6 +785,7 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
+        .ecc_irq = 28,
         .machine_id = 0x71,
         .iommu_version = 0x01000000,
         .intbit_to_level = {
@@ -824,6 +827,7 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
+        .ecc_irq = 28,
         .machine_id = 0x72,
         .iommu_version = 0x13000000,
         .intbit_to_level = {
Index: hw/sun4m.h
===================================================================
RCS file: /sources/qemu/qemu/hw/sun4m.h,v
retrieving revision 1.8
diff -p -u -r1.8 sun4m.h
--- hw/sun4m.h  1 Jan 2008 17:04:45 -0000       1.8
+++ hw/sun4m.h  6 Jan 2008 15:03:53 -0000
@@ -81,6 +81,6 @@ void lance_init(NICInfo *nd, target_phys
                 qemu_irq irq, qemu_irq *reset);
 
 /* eccmemctl.c */
-void *ecc_init(target_phys_addr_t base, uint32_t version);
+void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
 
 #endif