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Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system)
From: |
M. Warner Losh |
Subject: |
Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system) |
Date: |
Thu, 22 May 2008 10:17:15 -0600 (MDT) |
In message: <address@hidden>
Paul Brook <address@hidden> writes:
: > : > I know that Cavium/octeon board are MIPS CPU.
: > :
: > : Not really. They're MIPS with extra weirdness.
: >
: > All SoCs are MIPS with extra documented weirdness. The OCTEON CPUs
: > aren't documented in a public...
:
: The Cavium cores are weirder than most. It doesn't use the normal MIPS ISA.
: Most SoC are a standard mips core (r4k, etc.) with a bunch of peripherals.
Yes, they do use the noraml MIPS ISA. It is a MIPS64r2 part. It does
have a bunch of additional instructions that are leveraged off the CP2
coprocessor for crypto and related things. Its cache is different
too, but every platform's cache is different. There's a number of
hacks present to allow different images to run on different core.
Or maybe this is what you are saying :-
Warner
Re: [Qemu-devel] Support For Octeon/Cavium CPU (MIPS system), M. Warner Losh, 2008/05/22