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Re: [Qemu-devel] Re: [PATCH][ARM] Fix wrong destination register for smu

From: Vincent Palatin
Subject: Re: [Qemu-devel] Re: [PATCH][ARM] Fix wrong destination register for smuad, smusd, smlad, smlsd
Date: Wed, 25 Jun 2008 21:11:17 +0200
User-agent: KMail/1.9.7

Paul wrote:
> I'm generally more interested in the description/explanation of the patches
> themselves.  Saying "FOO works" is nice, but not as nice as convincing me
> that you understand both the code you're changing, the arm architecture,
> and that the two agree :-)

That's fairly right, but I'm not sure that the problem lays here.
Indeed, as Laurent mentioned in his mail on monday, my 2 previous patchs with 
fixes for ARM instructions were not integrated too while I hope I've put a 
fairly descriptive text with them ( I re-attach them if you have any comment)


---------- Forwarded message  ----------
Suject : [PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations

[PATCH] ARM: fix carry flags for ARMv6 unsigned SIMD operations
On ARMv6 emulation, I have caught some cases where the GE flags were
badly set after a "uadd8" operation.
After a quick code review, it seems to be a bad cut-n-paste between
16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by
pair instead of one at a time.
Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT
carry" instead of "carry" (probably once again due to a copy of the 
substraction code which sets flags to "NOT borrow")

I attach a patch to fix those issues. (arith_ge.patch)

---------- Forwarded message  ----------
Subject: [PATCH] ARM: fix CPS instruction

I attach a patch with 2 fixes for the ARMv6 instruction "CPS".
According to ARM Reference Manual (DDI0100 A4.1.16), 
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask 
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)

Attachment: arith_ge.patch
Description: Text Data

Attachment: arm_cps.patch
Description: Text Data

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