Re: [Qemu-devel] sparc 64-bit fsr problem

[Blue Swirl]

On 8/29/08, Vince Weaver <address@hidden> wrote:
>
>
> > I've attempted to fix this myself but I am having trouble trying to get
> the gen_mov_reg_FCC0() and gen_mov_reg_FCC1() functions in
> target-sparc/translate.c to use 64-bit shifts.

I think the fsr bit definitions in cpu.h need to be changed from 1<<x
to 1ULL << x, then the (target_ulong) cast should not be needed
anymore.

>  I've managed to get things working, at least enough to run equake from the
> spec2k benchmarks.  The patch is below.

Thanks for the debugging by the way!

>
>
>  Vince
>
>  --- op_helper.c.orig    2008-08-28 17:25:22.000000000 -0400
>  +++ op_helper.c 2008-08-28 17:27:42.000000000 -0400
>  @@ -746,10 +746,10 @@
>      {                                                                   \
>          target_ulong new_fsr;                                           \
>                                                                          \
>  -        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \
>  +        env->fsr &= ~((target_ulong) (FSR_FCC1 | FSR_FCC0) << FS);      \
>          switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \
>          case float_relation_unordered:                                  \
>  -            new_fsr = (FSR_FCC1 | FSR_FCC0) << FS;                      \
>  +            new_fsr = (target_ulong)(FSR_FCC1 | FSR_FCC0) << FS;        \
>              if ((env->fsr & FSR_NVM) || TRAP) {                         \
>                  env->fsr |= new_fsr;                                    \
>                  env->fsr |= FSR_NVC;                                    \
>  @@ -760,10 +760,10 @@
>              }                                                           \
>              break;                                                      \
>          case float_relation_less:                                       \
>  -            new_fsr = FSR_FCC0 << FS;                                   \
>  +            new_fsr = (target_ulong)FSR_FCC0 << FS;                     \
>              break;                                                      \
>          case float_relation_greater:                                    \
>  -            new_fsr = FSR_FCC1 << FS;                                   \
>  +          new_fsr = (target_ulong)FSR_FCC1 << FS;                      \
>              break;                                                      \
>          default:                                                        \
>              new_fsr = 0;                                                \
>  --- translate.c.orig    2008-08-29 15:59:15.000000000 -0400
>  +++ translate.c 2008-08-29 15:59:57.000000000 -0400
>  @@ -999,7 +999,7 @@
>   static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
>                                      unsigned int fcc_offset)
>   {
>  -    tcg_gen_extu_i32_tl(reg, src);
>  +    tcg_gen_mov_tl(reg, src);
>      tcg_gen_shri_tl(reg, reg, FSR_FCC0_SHIFT + fcc_offset);

Drop the mov and:
     tcg_gen_shri_tl(reg, src FSR_FCC0_SHIFT + fcc_offset);

>      tcg_gen_andi_tl(reg, reg, 0x1);
>   }
>  @@ -1007,7 +1007,7 @@
>   static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
>                                      unsigned int fcc_offset)
>   {
>  -    tcg_gen_extu_i32_tl(reg, src);
>  +    tcg_gen_mov_tl(reg, src);
>      tcg_gen_shri_tl(reg, reg, FSR_FCC1_SHIFT + fcc_offset);

Same here.

>      tcg_gen_andi_tl(reg, reg, 0x1);
>   }