[Qemu-devel] [PATCH v4 7/8] Add common keys to firmware configuration

[Gleb Natapov]

From: Blue Swirl <address@hidden>


---

 hw/fw_cfg.c |    4 +++
 hw/fw_cfg.h |    4 +++
 hw/pc.c     |    1 +
 hw/sun4m.c  |   77 ++++++++++++++++++++++++++++++++++++++++++++---------------
 hw/sun4u.c  |   10 ++++++++
 5 files changed, 77 insertions(+), 19 deletions(-)

diff --git a/hw/fw_cfg.c b/hw/fw_cfg.c
index 603613b..6ec69f1 100644
--- a/hw/fw_cfg.c
+++ b/hw/fw_cfg.c
@@ -197,6 +197,7 @@ void *fw_cfg_init(uint32_t port, target_phys_addr_t addr)
 {
     FWCfgState *s;
     int io_memory;
+    extern int nographic;
 
     s = qemu_mallocz(sizeof(FWCfgState));
     if (!s)
@@ -214,6 +215,9 @@ void *fw_cfg_init(uint32_t port, target_phys_addr_t addr)
     }
     fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
     fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
+    fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)nographic);
+    fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
+
     register_savevm("fw_cfg", -1, 1, fw_cfg_save, fw_cfg_load, s);
     qemu_register_reset(fw_cfg_reset, s);
     fw_cfg_reset(s);
diff --git a/hw/fw_cfg.h b/hw/fw_cfg.h
index 4db3563..6f28a05 100644
--- a/hw/fw_cfg.h
+++ b/hw/fw_cfg.h
@@ -4,6 +4,10 @@
 #define FW_CFG_SIGNATURE        0x00
 #define FW_CFG_ID               0x01
 #define FW_CFG_UUID             0x02
+#define FW_CFG_RAM_SIZE         0x03
+#define FW_CFG_NOGRAPHIC        0x04
+#define FW_CFG_NB_CPUS          0x05
+#define FW_CFG_MACHINE_ID       0x06
 #define FW_CFG_MAX_ENTRY        0x10
 
 #define FW_CFG_ARCH_LOCAL       0x8000
diff --git a/hw/pc.c b/hw/pc.c
index aae9fc6..040efe7 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -521,6 +521,7 @@ static void bochs_bios_init(void)
     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
     cpu_speed = (uint16_t)get_freq(1, 1);
     fw_cfg_add_i16(fw_cfg, FW_CFG_PC_CPUSPEED, cpu_speed);
+    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 }
 
 /* Generate an initial boot sector which sets state and jump to
diff --git a/hw/sun4m.c b/hw/sun4m.c
index 6f3108b..88bb0d4 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -101,7 +101,8 @@ struct hwdef {
     // register bit numbers
     int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
     int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
-    int machine_id; // For NVRAM
+    uint8_t nvram_machine_id;
+    uint16_t machine_id;
     uint32_t iommu_version;
     uint32_t intbit_to_level[32];
     uint64_t max_mem;
@@ -122,7 +123,8 @@ struct sun4d_hwdef {
     // IRQ numbers are not PIL ones, but SBI register bit numbers
     int esp_irq, le_irq, clock_irq, clock1_irq;
     int ser_irq, ms_kb_irq, me_irq;
-    int machine_id; // For NVRAM
+    uint8_t nvram_machine_id;
+    uint16_t machine_id;
     uint32_t iounit_version;
     uint64_t max_mem;
     const char * const default_cpu_model;
@@ -178,7 +180,7 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, 
const char *cmdline,
                        const char *boot_devices, ram_addr_t RAM_size,
                        uint32_t kernel_size,
                        int width, int height, int depth,
-                       int machine_id, const char *arch)
+                       int nvram_machine_id, const char *arch)
 {
     unsigned int i;
     uint32_t start, end;
@@ -251,7 +253,8 @@ static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, 
const char *cmdline,
     end = 0x1fd0;
     OpenBIOS_finish_partition(part_header, end - start);
 
-    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
+    Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
+                    nvram_machine_id);
 
     for (i = 0; i < sizeof(image); i++)
         m48t59_write(nvram, i, image[i]);
@@ -568,7 +571,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, 
ram_addr_t RAM_size,
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id,
+               "Sun4m");
 
     if (hwdef->ecc_base != (target_phys_addr_t)-1)
         ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
@@ -576,6 +580,8 @@ static void sun4m_hw_init(const struct hwdef *hwdef, 
ram_addr_t RAM_size,
 
     fw_cfg = fw_cfg_init(0, CFG_ADDR);
     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
+    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 }
 
 static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
@@ -721,12 +727,30 @@ static void sun4c_hw_init(const struct hwdef *hwdef, 
ram_addr_t RAM_size,
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id,
+               "Sun4c");
 
     fw_cfg = fw_cfg_init(0, CFG_ADDR);
     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
+    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 }
 
+enum {
+    ss2_id = 0,
+    ss5_id = 32,
+    vger_id,
+    lx_id,
+    ss4_id,
+    scls_id,
+    sbook_id,
+    ss10_id = 64,
+    ss20_id,
+    ss600mp_id,
+    ss1000_id = 96,
+    ss2000_id,
+};
+
 static const struct hwdef hwdefs[] = {
     /* SS-5 */
     {
@@ -761,7 +785,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = 5,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss5_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -805,7 +830,8 @@ static const struct hwdef hwdefs[] = {
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x72,
+        .nvram_machine_id = 0x72,
+        .machine_id = ss10_id,
         .iommu_version = 0x03000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -849,7 +875,8 @@ static const struct hwdef hwdefs[] = {
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x71,
+        .nvram_machine_id = 0x71,
+        .machine_id = ss600mp_id,
         .iommu_version = 0x01000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -893,7 +920,8 @@ static const struct hwdef hwdefs[] = {
         .me_irq = 30,
         .cs_irq = -1,
         .ecc_irq = 28,
-        .machine_id = 0x72,
+        .nvram_machine_id = 0x72,
+        .machine_id = ss20_id,
         .iommu_version = 0x13000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -933,7 +961,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 1,
         .me_irq = 1,
         .cs_irq = -1,
-        .machine_id = 0x55,
+        .nvram_machine_id = 0x55,
+        .machine_id = ss2_id,
         .max_mem = 0x10000000,
         .default_cpu_model = "Cypress CY7C601",
     },
@@ -970,7 +999,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = vger_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1012,7 +1042,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = lx_id,
         .iommu_version = 0x04000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1054,7 +1085,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = 5,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss4_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1096,7 +1128,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = scls_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1138,7 +1171,8 @@ static const struct hwdef hwdefs[] = {
         .fd_irq = 22,
         .me_irq = 30,
         .cs_irq = -1,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = sbook_id,
         .iommu_version = 0x05000000,
         .intbit_to_level = {
             2, 3, 5, 7, 9, 11, 0, 14,   3, 5, 7, 9, 11, 13, 12, 12,
@@ -1359,7 +1393,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
         .clock1_irq = 10,
         .ms_kb_irq = 12,
         .ser_irq = 12,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss1000_id,
         .iounit_version = 0x03000000,
         .max_mem = 0xf00000000ULL,
         .default_cpu_model = "TI SuperSparc II",
@@ -1392,7 +1427,8 @@ static const struct sun4d_hwdef sun4d_hwdefs[] = {
         .clock1_irq = 10,
         .ms_kb_irq = 12,
         .ser_irq = 12,
-        .machine_id = 0x80,
+        .nvram_machine_id = 0x80,
+        .machine_id = ss2000_id,
         .iounit_version = 0x03000000,
         .max_mem = 0xf00000000ULL,
         .default_cpu_model = "TI SuperSparc II",
@@ -1538,10 +1574,13 @@ static void sun4d_hw_init(const struct sun4d_hwdef 
*hwdef, ram_addr_t RAM_size,
 
     nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
                boot_device, RAM_size, kernel_size, graphic_width,
-               graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
+               graphic_height, graphic_depth, hwdef->nvram_machine_id,
+               "Sun4d");
 
     fw_cfg = fw_cfg_init(0, CFG_ADDR);
     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
+    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 }
 
 /* SPARCserver 1000 hardware initialisation */
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 4bac0d6..8cd8443 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -49,6 +49,7 @@
 
 struct hwdef {
     const char * const default_cpu_model;
+    uint16_t machine_id;
 };
 
 int DMA_get_channel_mode (int nchan)
@@ -420,16 +421,25 @@ static void sun4uv_init(ram_addr_t RAM_size, int 
vga_ram_size,
 
     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, 0);
     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
+    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
+    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 }
 
+enum {
+    sun4u_id = 0,
+    sun4v_id = 64,
+};
+
 static const struct hwdef hwdefs[] = {
     /* Sun4u generic PC-like machine */
     {
         .default_cpu_model = "TI UltraSparc II",
+        .machine_id = sun4u_id,
     },
     /* Sun4v generic PC-like machine */
     {
         .default_cpu_model = "Sun UltraSparc T1",
+        .machine_id = sun4v_id,
     },
 };