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[Qemu-devel] [5218] ppc: Convert op_andi to TCG
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [5218] ppc: Convert op_andi to TCG |
Date: |
Sun, 14 Sep 2008 18:30:32 +0000 |
Revision: 5218
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5218
Author: aurel32
Date: 2008-09-14 18:30:32 +0000 (Sun, 14 Sep 2008)
Log Message:
-----------
ppc: Convert op_andi to TCG
Replace op_andi_... with tcg_gen_andi_tl.
Signed-off-by: Andreas Faerber <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Modified Paths:
--------------
trunk/target-ppc/op.c
trunk/target-ppc/translate.c
Modified: trunk/target-ppc/op.c
===================================================================
--- trunk/target-ppc/op.c 2008-09-14 18:30:23 UTC (rev 5217)
+++ trunk/target-ppc/op.c 2008-09-14 18:30:32 UTC (rev 5218)
@@ -1153,33 +1153,6 @@
RETURN();
}
-/* andi. */
-void OPPROTO op_andi_T0 (void)
-{
- T0 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-void OPPROTO op_andi_T1 (void)
-{
- T1 &= (uint32_t)PARAM1;
- RETURN();
-}
-
-#if defined(TARGET_PPC64)
-void OPPROTO op_andi_T0_64 (void)
-{
- T0 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-
-void OPPROTO op_andi_T1_64 (void)
-{
- T1 &= ((uint64_t)PARAM1 << 32) | (uint64_t)PARAM2;
- RETURN();
-}
-#endif
-
/* count leading zero */
void OPPROTO op_cntlzw (void)
{
Modified: trunk/target-ppc/translate.c
===================================================================
--- trunk/target-ppc/translate.c 2008-09-14 18:30:23 UTC (rev 5217)
+++ trunk/target-ppc/translate.c 2008-09-14 18:30:32 UTC (rev 5218)
@@ -1235,7 +1235,7 @@
GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode));
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1243,7 +1243,7 @@
GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
{
tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
- gen_op_andi_T0(UIMM(ctx->opcode) << 16);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], UIMM(ctx->opcode) << 16);
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
gen_set_Rc0(ctx);
}
@@ -1458,8 +1458,8 @@
me += 32;
#endif
mask = MASK(mb, me);
- gen_op_andi_T0(mask);
- gen_op_andi_T1(~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -1498,7 +1498,7 @@
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1519,7 +1519,7 @@
mb += 32;
me += 32;
#endif
- gen_op_andi_T0(MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1558,22 +1558,6 @@
gen_##name(ctx, 1, 1); \
}
-static always_inline void gen_andi_T0_64 (DisasContext *ctx, uint64_t mask)
-{
- if (mask >> 32)
- gen_op_andi_T0_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T0(mask);
-}
-
-static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
-{
- if (mask >> 32)
- gen_op_andi_T1_64(mask >> 32, mask & 0xFFFFFFFF);
- else
- gen_op_andi_T1(mask);
-}
-
static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
uint32_t me, uint32_t sh)
{
@@ -1597,7 +1581,7 @@
}
gen_op_rotli64_T0(sh);
do_mask:
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1641,7 +1625,7 @@
tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
gen_op_rotl64_T0_T1();
if (unlikely(mb != 0 || me != 63)) {
- gen_andi_T0_64(ctx, MASK(mb, me));
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], MASK(mb, me));
}
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
if (unlikely(Rc(ctx->opcode) != 0))
@@ -1689,8 +1673,8 @@
gen_op_rotli64_T0(sh);
do_mask:
mask = MASK(mb, me);
- gen_andi_T0_64(ctx, mask);
- gen_andi_T1_64(ctx, ~mask);
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], mask);
+ tcg_gen_andi_tl(cpu_T[1], cpu_T[1], ~mask);
gen_op_or();
do_store:
tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
@@ -3107,7 +3091,7 @@
gen_op_sli_T1(-sh); \
gen_op_##op(); \
bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
- gen_op_andi_T0(bitmask); \
+ tcg_gen_andi_tl(cpu_T[0], cpu_T[0], bitmask); \
tcg_gen_andi_i32(cpu_T[1], cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
gen_op_or(); \
tcg_gen_andi_i32(cpu_crf[crbD(ctx->opcode) >> 2], cpu_T[0], 0xf); \
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