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[Qemu-devel] [5303] Use concet TCG instructions in the MIPS target.
From: |
Thiemo Seufer |
Subject: |
[Qemu-devel] [5303] Use concet TCG instructions in the MIPS target. |
Date: |
Mon, 22 Sep 2008 21:54:01 +0000 |
Revision: 5303
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=5303
Author: ths
Date: 2008-09-22 21:54:00 +0000 (Mon, 22 Sep 2008)
Log Message:
-----------
Use concet TCG instructions in the MIPS target.
Signed-off-by: Thiemo Seufer <address@hidden>
Modified Paths:
--------------
trunk/target-mips/translate.c
Modified: trunk/target-mips/translate.c
===================================================================
--- trunk/target-mips/translate.c 2008-09-22 20:51:28 UTC (rev 5302)
+++ trunk/target-mips/translate.c 2008-09-22 21:54:00 UTC (rev 5303)
@@ -2129,7 +2129,6 @@
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
@@ -2138,11 +2137,7 @@
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2160,7 +2155,6 @@
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2169,11 +2163,7 @@
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_add_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2191,7 +2181,6 @@
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32s_tl(t0, t0);
tcg_gen_ext32s_tl(t1, t1);
@@ -2200,11 +2189,7 @@
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
@@ -2222,7 +2207,6 @@
{
TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
- TCGv r_tmp3 = tcg_temp_new(TCG_TYPE_I64);
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2231,11 +2215,7 @@
tcg_gen_mul_i64(r_tmp1, r_tmp1, r_tmp2);
gen_load_LO(t0, 0);
gen_load_HI(t1, 0);
- tcg_gen_extu_tl_i64(r_tmp2, t0);
- tcg_gen_extu_tl_i64(r_tmp3, t1);
- tcg_gen_shli_i64(r_tmp3, r_tmp3, 32);
- tcg_gen_or_i64(r_tmp2, r_tmp2, r_tmp3);
- tcg_temp_free(r_tmp3);
+ tcg_gen_concat_tl_i64(r_tmp2, t0, t1);
tcg_gen_sub_i64(r_tmp1, r_tmp1, r_tmp2);
tcg_temp_free(r_tmp2);
tcg_gen_trunc_i64_tl(t0, r_tmp1);
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