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[Qemu-devel] [PATCH 02/11] target-mips: optimize gen_op_addr_add() (1/2)
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 02/11] target-mips: optimize gen_op_addr_add() (1/2) |
Date: |
Sat, 8 Nov 2008 09:32:57 +0100 |
User-agent: |
Mutt/1.5.18 (2008-05-17) |
The user mode can be tested at translation time using ctx->hflags.
This simplifies gen_op_addr_add().
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 16 ++++++----------
1 files changed, 6 insertions(+), 10 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index dcd8094..cbe8120 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -894,7 +894,7 @@ generate_exception (DisasContext *ctx, int excp)
}
/* Addresses computation */
-static inline void gen_op_addr_add (TCGv t0, TCGv t1)
+static inline void gen_op_addr_add (DisasContext *ctx, TCGv t0, TCGv t1)
{
tcg_gen_add_tl(t0, t0, t1);
@@ -902,17 +902,13 @@ static inline void gen_op_addr_add (TCGv t0, TCGv t1)
/* For compatibility with 32-bit code, data reference in user mode
with Status_UX = 0 should be casted to 32-bit and sign extended.
See the MIPS64 PRA manual, section 4.10. */
- {
+ if ((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) {
int l1 = gen_new_label();
- TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
+ TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
- tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
- tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
- tcg_temp_free(r_tmp);
tcg_gen_ext32s_i64(t0, t0);
gen_set_label(l1);
}
@@ -1070,7 +1066,7 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc,
int rt,
} else {
gen_load_gpr(t0, base);
tcg_gen_movi_tl(t1, offset);
- gen_op_addr_add(t0, t1);
+ gen_op_addr_add(ctx, t0, t1);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
@@ -1235,7 +1231,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
gen_load_gpr(t0, base);
tcg_gen_movi_tl(t1, offset);
- gen_op_addr_add(t0, t1);
+ gen_op_addr_add(ctx, t0, t1);
tcg_temp_free(t1);
}
/* Don't do NOP if destination is zero: we must perform the actual
@@ -7369,7 +7365,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t
opc,
} else {
gen_load_gpr(t0, base);
gen_load_gpr(t1, index);
- gen_op_addr_add(t0, t1);
+ gen_op_addr_add(ctx, t0, t1);
}
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
--
1.5.6.5
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' address@hidden | address@hidden
`- people.debian.org/~aurel32 | www.aurel32.net
- [Qemu-devel] [PATCH 0/11] target-mips: optimizations, Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 01/11] target-mips: optimize gen_save_pc(), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 02/11] target-mips: optimize gen_op_addr_add() (1/2),
Aurelien Jarno <=
- [Qemu-devel] [PATCH 03/11] target-mips: optimize gen_op_addr_add() (2/2), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 04/11] target-mips: convert bitfield ops to TCG, Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 05/11] target-mips: convert bit shuffle ops to TCG, Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 06/11] target-mips: optimize gen_arith()/gen_arith_imm(), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 07/11] target-mips: optimize gen_muldiv(), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 08/11] target-mips: optimize gen_farith(), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 09/11] target-mips: optimize movc*(), Aurelien Jarno, 2008/11/08
- [Qemu-devel] [PATCH 10/11] target-mips: gen_compute_branch1(), Aurelien Jarno, 2008/11/08