[Qemu-devel] [PATCH 1/2] Add HPET emulation to qemu (v4)

[Beth Kon]

This version includes -

- required Interrupt Source Override changes
- incorporation of comments from v3
- added -no-hpet option
- added info hpet to monitor for checking whether hpet is active
- bugfix for system reset (handoff between pit/hpet)
- enabled 64-bit capability (after discovering that OS is 
  warned in HPET spec about possibility that a 64-bit read may 
  be implemented as two 32-bit reads).
- added wrap interrupt for one-shot 32 bit timers, as dictated 
  by HPET spec. (Interrupt on wrap in addition to interrupt on
  timer expiration)

One area that needs special attention:  

The HPET Timer N Configuration and Capability register contains a field
that advertises which IOAPIC interrupts are available for routing of the
timer's interrupt. I hunted around in the QEMU code and found that
pretty much all of those that map to both PIC and IOAPIC are already in
use. In legacy mode, timer 0 uses INTI2 and timer 1 uses INTI8,
replacing PIT and RTC. But when not in legacy mode, I assume I need to
advertise at least 3 values. I chose 5, 10 and 11 (trying to choose more
obscure options), but am not sure that will work for all configurations.

As I understand the code, IOAPIC_NUM_PINS = 18, and we are only mapping
the PIC IRQs, 0-15, so maybe we need to enable the use of pins 16 and
17? Or do we need to increase the size of the IOAPIC? (HPET requires
interrupt routing to the IOAPIC but not to the 8259). Comments?

The first patch contains changes to QEMU, the second patch contains
changes to BOCHS BIOS.

Signed-off-by Beth Kon <address@hidden>


-- 
Elizabeth Kon (Beth)
IBM Linux Technology Center
Open Hypervisor Team
email: address@hidden

qemu_hpet_v4.patch
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