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[Qemu-devel] [PATCH v5 17/18] gdbstub: x86: Support for setting segment
From: |
Jan Kiszka |
Subject: |
[Qemu-devel] [PATCH v5 17/18] gdbstub: x86: Support for setting segment registers |
Date: |
Mon, 17 Nov 2008 17:18:59 +0100 |
User-agent: |
StGIT/0.14.2 |
This allows to set segment registers via gdb also in system emulation
mode. Basic sanity checks are applied and nothing is changed if they
fail. But screwing up the target via this interface will never be
complicated, so I avoided being too paranoid here.
Signed-off-by: Jan Kiszka <address@hidden>
---
gdbstub.c | 60 ++++++++++++++++++++++++++++++++++-------------
target-i386/cpu.h | 14 +++++++++++
target-i386/op_helper.c | 14 -----------
3 files changed, 57 insertions(+), 31 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index fd4d5db..c83b76a 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -358,6 +358,43 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t
*mem_buf, int n)
return 0;
}
+static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
+{
+ uint16_t selector = ldl_p(mem_buf);
+
+ if (selector != env->segs[sreg].selector) {
+#if defined(CONFIG_USER_ONLY)
+ cpu_x86_load_seg(env, sreg, selector);
+#else
+ SegmentCache *dt;
+ target_ulong ptr;
+ uint32_t e1, e2;
+ int index;
+
+ if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
+ cpu_x86_load_seg_cache(env, sreg, selector, selector << 4,
+ 0xffff, 0);
+ } else {
+ if (selector & 0x4)
+ dt = &env->ldt;
+ else
+ dt = &env->gdt;
+ index = selector & ~7;
+ ptr = dt->base + index;
+ if ((index + 7) <= dt->limit &&
+ cpu_memory_rw_debug(env, ptr, (uint8_t *)&e1,
+ sizeof(e1), 0) == 0 &&
+ cpu_memory_rw_debug(env, ptr + 4, (uint8_t *)&e2,
+ sizeof(e2), 0) == 0)
+ cpu_x86_load_seg_cache(env, sreg, selector,
+ get_seg_base(e1, e2),
+ get_seg_limit(e1, e2), e2);
+ }
+#endif
+ }
+ return 4;
+}
+
static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
{
uint32_t tmp;
@@ -385,23 +422,12 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t
*mem_buf, int n)
env->eflags = ldl_p(mem_buf);
return 4;
-#if defined(CONFIG_USER_ONLY)
-#define LOAD_SEG(index, sreg)\
- tmp = ldl_p(mem_buf);\
- if (tmp != env->segs[sreg].selector)\
- cpu_x86_load_seg(env, sreg, tmp);\
- return 4
-#else
-/* FIXME: Honor segment registers. Needs to avoid raising an exception
- when the selector is invalid. */
-#define LOAD_SEG(index, sreg) return 4
-#endif
- case IDX_SEG_REGS: LOAD_SEG(10, R_CS);
- case IDX_SEG_REGS + 1: LOAD_SEG(11, R_SS);
- case IDX_SEG_REGS + 2: LOAD_SEG(12, R_DS);
- case IDX_SEG_REGS + 3: LOAD_SEG(13, R_ES);
- case IDX_SEG_REGS + 4: LOAD_SEG(14, R_FS);
- case IDX_SEG_REGS + 5: LOAD_SEG(15, R_GS);
+ case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
+ case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
+ case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
+ case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
+ case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
+ case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
case IDX_FP_REGS + 8:
env->fpuc = ldl_p(mem_buf);
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index eed1f62..b7c8a2f 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -651,6 +651,20 @@ int cpu_get_pic_interrupt(CPUX86State *s);
/* MSDOS compatibility mode FPU exception support */
void cpu_set_ferr(CPUX86State *s);
+static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
+{
+ unsigned int limit;
+ limit = (e1 & 0xffff) | (e2 & 0x000f0000);
+ if (e2 & DESC_G_MASK)
+ limit = (limit << 12) | 0xfff;
+ return limit;
+}
+
+static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
+{
+ return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
+}
+
/* this function must always be used to load data in the segment
cache: it synchronizes the hflags with the segment cache values */
static inline void cpu_x86_load_seg_cache(CPUX86State *env,
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 6dc0802..091dc97 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -143,20 +143,6 @@ static inline int load_segment(uint32_t *e1_ptr, uint32_t
*e2_ptr,
return 0;
}
-static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2)
-{
- unsigned int limit;
- limit = (e1 & 0xffff) | (e2 & 0x000f0000);
- if (e2 & DESC_G_MASK)
- limit = (limit << 12) | 0xfff;
- return limit;
-}
-
-static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2)
-{
- return ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
-}
-
static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1,
uint32_t e2)
{
sc->base = get_seg_base(e1, e2);
- [Qemu-devel] [PATCH v5 00/18] Enhance debugging support, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 05/18] Set mem_io_vaddr on io_read, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 12/18] Introduce BP_CPU as a breakpoint type, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 03/18] gdbstub: Return appropriate watch message to gdb, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 13/18] x86: Debug register emulation, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 04/18] Refactor and enhance break/watchpoint API, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 15/18] gdbstub: Add vCont support, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 17/18] gdbstub: x86: Support for setting segment registers,
Jan Kiszka <=
- [Qemu-devel] [PATCH v5 01/18] Convert CPU_PC_FROM_TB to static inline, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 06/18] Respect length of watchpoints, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 14/18] x86: Dump debug registers, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 11/18] Add debug exception hook, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 10/18] Introduce BP_WATCHPOINT_HIT flag, Jan Kiszka, 2008/11/17
- [Qemu-devel] [PATCH v5 18/18] gdbstub: x86: Switch 64/32 bit registers dynamically, Jan Kiszka, 2008/11/17