[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] SH: Improve the interrupt controller

From: Vladimir Prus
Subject: [Qemu-devel] SH: Improve the interrupt controller
Date: Thu, 11 Dec 2008 22:52:17 +0300
User-agent: KMail/1.9.10

This patch improves the intc implementation in these ways:

   - On interrupt, the priority mask in SSR is updated,
     if OPM register tells it should be
   - We check interrupt priority and compare it with
     priority mask
   - Priorities for IRL interrupts (which are fixed), are
   - The ICR register is supported, and LVLMODE bit, which
     controls if interrupt is automatically de-asserted,
     is implemented
   - A bug where handling of paired set mask / clear mask
     registers was done backward is fixed
   - A bug where enabling a group did not work was fixed.

I have tested this only with SH4A and it's desirable to test
with 7751/R2D. However, I no longer sure I know which kernel
to use for that. Can anybody either provide me with instructions,
or test this patch with R2D for me?

- Volodya

Attachment: intc.diff
Description: Text Data

reply via email to

[Prev in Thread] Current Thread [Next in Thread]