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[Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes.
From: |
Tristan Gingold |
Subject: |
[Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes. |
Date: |
Tue, 24 Mar 2009 16:47:51 +0100 |
This is necessary for alpha because it has 4 protection levels and pal mode.
Signed-off-by: Tristan Gingold <address@hidden>
---
exec.c | 30 +++++++++++++++++++++++++-----
softmmu_exec.h | 29 ++++++++++++++++++++++++-----
2 files changed, 49 insertions(+), 10 deletions(-)
diff --git a/exec.c b/exec.c
index 12d35b0..472b6c4 100644
--- a/exec.c
+++ b/exec.c
@@ -1760,12 +1760,18 @@ void tlb_flush(CPUState *env, int flush_global)
env->tlb_table[2][i].addr_read = -1;
env->tlb_table[2][i].addr_write = -1;
env->tlb_table[2][i].addr_code = -1;
-#if (NB_MMU_MODES == 4)
+#endif
+#if (NB_MMU_MODES >= 4)
env->tlb_table[3][i].addr_read = -1;
env->tlb_table[3][i].addr_write = -1;
env->tlb_table[3][i].addr_code = -1;
#endif
+#if (NB_MMU_MODES >= 5)
+ env->tlb_table[4][i].addr_read = -1;
+ env->tlb_table[4][i].addr_write = -1;
+ env->tlb_table[4][i].addr_code = -1;
#endif
+
}
memset (env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
@@ -1809,9 +1815,12 @@ void tlb_flush_page(CPUState *env, target_ulong addr)
tlb_flush_entry(&env->tlb_table[1][i], addr);
#if (NB_MMU_MODES >= 3)
tlb_flush_entry(&env->tlb_table[2][i], addr);
-#if (NB_MMU_MODES == 4)
+#endif
+#if (NB_MMU_MODES >= 4)
tlb_flush_entry(&env->tlb_table[3][i], addr);
#endif
+#if (NB_MMU_MODES >= 5)
+ tlb_flush_entry(&env->tlb_table[4][i], addr);
#endif
tlb_flush_jmp_cache(env, addr);
@@ -1895,10 +1904,14 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start,
ram_addr_t end,
#if (NB_MMU_MODES >= 3)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[2][i], start1, length);
-#if (NB_MMU_MODES == 4)
+#endif
+#if (NB_MMU_MODES >= 4)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_reset_dirty_range(&env->tlb_table[3][i], start1, length);
#endif
+#if (NB_MMU_MODES >= 5)
+ for(i = 0; i < CPU_TLB_SIZE; i++)
+ tlb_reset_dirty_range(&env->tlb_table[4][i], start1, length);
#endif
}
}
@@ -1944,10 +1957,14 @@ void cpu_tlb_update_dirty(CPUState *env)
#if (NB_MMU_MODES >= 3)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[2][i]);
-#if (NB_MMU_MODES == 4)
+#endif
+#if (NB_MMU_MODES >= 4)
for(i = 0; i < CPU_TLB_SIZE; i++)
tlb_update_dirty(&env->tlb_table[3][i]);
#endif
+#if (NB_MMU_MODES >= 5)
+ for(i = 0; i < CPU_TLB_SIZE; i++)
+ tlb_update_dirty(&env->tlb_table[4][i]);
#endif
}
@@ -1969,9 +1986,12 @@ static inline void tlb_set_dirty(CPUState *env,
target_ulong vaddr)
tlb_set_dirty1(&env->tlb_table[1][i], vaddr);
#if (NB_MMU_MODES >= 3)
tlb_set_dirty1(&env->tlb_table[2][i], vaddr);
-#if (NB_MMU_MODES == 4)
+#endif
+#if (NB_MMU_MODES >= 4)
tlb_set_dirty1(&env->tlb_table[3][i], vaddr);
#endif
+#if (NB_MMU_MODES >= 5)
+ tlb_set_dirty1(&env->tlb_table[4][i], vaddr);
#endif
}
diff --git a/softmmu_exec.h b/softmmu_exec.h
index 9cc4535..8eaa0ad 100644
--- a/softmmu_exec.h
+++ b/softmmu_exec.h
@@ -60,6 +60,7 @@
#include "softmmu_header.h"
#undef ACCESS_TYPE
#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 3) */
#if (NB_MMU_MODES >= 4)
@@ -78,12 +79,30 @@
#include "softmmu_header.h"
#undef ACCESS_TYPE
#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 4) */
-#if (NB_MMU_MODES > 4)
-#error "NB_MMU_MODES > 4 is not supported for now"
-#endif /* (NB_MMU_MODES > 4) */
-#endif /* (NB_MMU_MODES == 4) */
-#endif /* (NB_MMU_MODES >= 3) */
+#if (NB_MMU_MODES >= 5)
+
+#define ACCESS_TYPE 4
+#define MEMSUFFIX MMU_MODE4_SUFFIX
+#define DATA_SIZE 1
+#include "softmmu_header.h"
+
+#define DATA_SIZE 2
+#include "softmmu_header.h"
+
+#define DATA_SIZE 4
+#include "softmmu_header.h"
+
+#define DATA_SIZE 8
+#include "softmmu_header.h"
+#undef ACCESS_TYPE
+#undef MEMSUFFIX
+#endif /* (NB_MMU_MODES >= 4) */
+
+#if (NB_MMU_MODES > 5)
+#error "NB_MMU_MODES > 5 is not supported for now"
+#endif /* (NB_MMU_MODES > 5) */
/* these access are slower, they must be as rare as possible */
#define ACCESS_TYPE (NB_MMU_MODES)
--
1.6.2
- [Qemu-devel] [PATCH 0/25]: add alpha es40 system emulation (v3), Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 01/25] Add support for multi-level phys map., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 02/25] Fix bug: palcode is at least 6 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 03/25] Fix bug: do not mask address LSBs for ldwu., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 04/25] Fix bug: integer conditionnal branch offset is 21 bits wide., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 05/25] bug fix: avoid nop to override next instruction, Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 06/25] Fix temp free for hw_st, Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 07/25] Increase Alpha physical address size to 44 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 08/25] Alpha: set target page size to 13 bits., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 09/25] Allow 5 mmu indexes.,
Tristan Gingold <=
- [Qemu-devel] [PATCH 10/25] Split cpu_mmu_index into cpu_mmu_index_data and cpu_mmu_index_code., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 11/25] Add square wave output support., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 12/25] Add ali1543 super IO pci device., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 13/25] Add 21272 chipset (memory and pci controller for alpha), Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 14/25] Add target-alpha/machine.c and hw/es40.c for es40 machine emulation., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 15/25] Move softmmu_helper.h from exec.h to op_helper.c on alpha., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 16/25] Document which IPR are used by 21264, Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 17/25] tb_flush helper should flush the tb (and not the tlb)., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 18/25] Add instruction name in comments for hw_ld opcode., Tristan Gingold, 2009/03/24
- [Qemu-devel] [PATCH 19/25] Remove PALCODE_ declarations (unused)., Tristan Gingold, 2009/03/24