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[Qemu-devel] [PATCH 1/1] PCI Memory Mapping
From: |
Brian Wheeler |
Subject: |
[Qemu-devel] [PATCH 1/1] PCI Memory Mapping |
Date: |
Mon, 06 Apr 2009 08:58:23 -0400 |
This patch
* modifies pci_to_cpu_addr() to support device-bus location mapping
* adds pci_register_physical_memory and pci_register_physical_memory_offset
* modifies cirrus_vga to use pci_register_physical_memory
The problem comes in with the alpha_softmmu target: pci_mem_base isn't
a static offset. On the alpha the base is defined as:
(0x80000000000ULL | (pci_dev->bus->bus_num * 0x200000000ULL) | addr
So, when a device is put into the system, its pci_mem_base address
depends on which bus it is put into.
This patch only handles cpu->pci memory access. It doesn't do anything
with DMA operations by the device.
I'd really like some feedback on this, since its pretty important for
the alpha_softmmu target.
Thanks!
Brian
Signed-off-by: Brian Wheeler <address@hidden>
---------------
Index: hw/cirrus_vga.c
===================================================================
--- hw/cirrus_vga.c (revision 7006)
+++ hw/cirrus_vga.c (working copy)
@@ -3327,9 +3327,9 @@
vga_dirty_log_stop((VGAState *)s);
/* XXX: add byte swapping apertures */
- cpu_register_physical_memory(addr, s->vram_size,
+ pci_register_physical_memory(d, addr, s->vram_size,
s->cirrus_linear_io_addr);
- cpu_register_physical_memory(addr + 0x1000000, 0x400000,
+ pci_register_physical_memory(d, addr + 0x1000000, 0x400000,
s->cirrus_linear_bitblt_io_addr);
s->map_addr = s->map_end = 0;
Index: hw/pci.c
===================================================================
--- hw/pci.c (revision 7006)
+++ hw/pci.c (working copy)
@@ -273,11 +273,29 @@
return pci_dev;
}
-static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
+static target_phys_addr_t pci_to_cpu_addr(PCIDevice *pci_dev,
+ target_phys_addr_t addr)
{
+#ifdef TARGET_ALPHA
+ return (0x80000000000ULL | (pci_dev->bus->bus_num * 0x200000000ULL) | addr;
+#else
return addr + pci_mem_base;
+#endif
}
+
+void pci_register_physical_memory_offset(PCIDevice *pci_dev,
+ target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset)
+{
+ start_addr = pci_to_cpu_addr(pci_dev, start_addr);
+ cpu_register_physical_memory_offset(start_addr, size, phys_offset,
+ region_offset);
+}
+
+
static void pci_unregister_io_regions(PCIDevice *pci_dev)
{
PCIIORegion *r;
@@ -290,7 +308,7 @@
if (r->type == PCI_ADDRESS_SPACE_IO) {
isa_unassign_ioport(r->addr, r->size);
} else {
- cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
+ cpu_register_physical_memory(pci_to_cpu_addr(pci_dev, r->addr),
r->size,
IO_MEM_UNASSIGNED);
}
@@ -409,7 +427,8 @@
isa_unassign_ioport(r->addr, r->size);
}
} else {
- cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
+ cpu_register_physical_memory(pci_to_cpu_addr(d,
+ r->addr),
r->size,
IO_MEM_UNASSIGNED);
qemu_unregister_coalesced_mmio(r->addr, r->size);
Index: hw/pci.h
===================================================================
--- hw/pci.h (revision 7006)
+++ hw/pci.h (working copy)
@@ -213,6 +213,25 @@
cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
}
+
+
+void pci_register_physical_memory_offset(PCIDevice *pci_dev,
+ target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset,
+ ram_addr_t region_offset);
+static inline void pci_register_physical_memory(PCIDevice *pci_dev,
+ target_phys_addr_t start_addr,
+ ram_addr_t size,
+ ram_addr_t phys_offset)
+{
+ pci_register_physical_memory_offset(pci_dev, start_addr, size,
+ phys_offset, 0);
+}
+
+
+
+
/* lsi53c895a.c */
#define LSI_MAX_DEVS 7
void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
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