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[Qemu-devel] [PATCH 16/16] Add two boards which use S3C2410 SOC
From: |
Vincent Sanders |
Subject: |
[Qemu-devel] [PATCH 16/16] Add two boards which use S3C2410 SOC |
Date: |
Thu, 23 Apr 2009 19:17:02 +0100 |
User-agent: |
Mutt/1.5.17+20080114 (2008-01-14) |
Add bast and smdk2410 boards which use S3C2410 SOC
Signed-off-by: Vincent Sanders <address@hidden>
---
Makefile.target | 1
hw/bast.c | 176 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/boards.h | 6 +
hw/smdk2410.c | 120 ++++++++++++++++++++++++++++++++++
target-arm/machine.c | 2
5 files changed, 305 insertions(+)
diff -urN qemusvnclean/hw/bast.c qemusvnpatches/hw/bast.c
--- qemusvnclean/hw/bast.c 1970-01-01 01:00:00.000000000 +0100
+++ qemusvnpatches/hw/bast.c 2009-04-23 17:45:53.000000000 +0100
@@ -0,0 +1,176 @@
+/* hw/bast.c
+ *
+ * System emulation for the Simtec Electronics BAST
+ *
+ * Copyright 2006, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#include "hw.h"
+#include "sysemu.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "smbus.h"
+#include "flash.h"
+#include "devices.h"
+#include "boards.h"
+
+#include "s3c2410x.h"
+
+#define BIOS_FILENAME "able.bin"
+
+typedef struct {
+ S3CState *soc;
+ unsigned char cpld_ctrl2;
+ struct nand_flash_s *nand[4];
+} STCBState;
+
+/* Bytes in a Kilobyte */
+#define KILO 1024
+/* Bytes in a megabyte */
+#define MEGA 1024 * KILO
+/* Bytes */
+#define BYTE 1
+/* Bits in a byte */
+#define BIT 8
+
+/* Useful defines */
+#define BAST_NOR_BASE CPU_S3C2410X_CS0
+#define BAST_NOR_SIZE 16 * MEGA / BIT
+#define BAST_BOARD_ID 331
+
+#define BAST_CS1_CPLD_BASE ((target_phys_addr_t)(CPU_S3C2410X_CS1 | (0xc <<
23)))
+#define BAST_CS5_CPLD_BASE ((target_phys_addr_t)(CPU_S3C2410X_CS5 | (0xc <<
23)))
+#define BAST_CPLD_SIZE (4<<23)
+
+static uint32_t cpld_read(void *opaque, target_phys_addr_t address)
+{
+ STCBState *stcb = (STCBState *)opaque;
+ int reg = (address >> 23) & 0xf;
+ if (reg == 0xc)
+ return stcb->cpld_ctrl2;
+ return 0;
+}
+
+static void cpld_write(void *opaque, target_phys_addr_t address,
+ uint32_t value)
+{
+ STCBState *stcb = (STCBState *)opaque;
+ int reg = (address >> 23) & 0xf;
+ if (reg == 0xc) {
+ stcb->cpld_ctrl2 = value;
+ s3c24xx_nand_attach(stcb->soc, stcb->nand[stcb->cpld_ctrl2 & 3]);
+ }
+}
+
+static CPUReadMemoryFunc *cpld_readfn[] = {
+ cpld_read,
+ cpld_read,
+ cpld_read
+};
+
+static CPUWriteMemoryFunc *cpld_writefn[] = {
+ cpld_write,
+ cpld_write,
+ cpld_write
+};
+
+static void stcb_cpld_register(STCBState *stcb)
+{
+ int tag = cpu_register_io_memory(0, cpld_readfn, cpld_writefn, stcb);
+ cpu_register_physical_memory(BAST_CS1_CPLD_BASE, BAST_CPLD_SIZE, tag);
+ cpu_register_physical_memory(BAST_CS5_CPLD_BASE, BAST_CPLD_SIZE, tag);
+ stcb->cpld_ctrl2 = 0;
+}
+
+static void stcb_i2c_setup(STCBState *stcb)
+{
+ i2c_bus *bus = s3c24xx_i2c_bus(stcb->soc->iic);
+}
+
+static struct arm_boot_info bast_binfo = {
+ .board_id = BAST_BOARD_ID,
+ .ram_size = 0x10000000, /* 256MB */
+};
+
+static void stcb_init(ram_addr_t _ram_size,
+ int vga_ram_size,
+ const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ STCBState *stcb;
+ int ret, index;
+
+ /* ensure memory is limited to 256MB */
+ if (_ram_size > (256 * MEGA * BYTE))
+ _ram_size = 256 * MEGA * BYTE;
+ ram_size = _ram_size;
+
+ /* allocate storage for board state */
+ stcb = malloc(sizeof(STCBState));
+
+ /* initialise SOC */
+ stcb->soc = s3c2410x_init(ram_size);
+
+ /* Register the NOR flash ROM */
+ cpu_register_physical_memory(BAST_NOR_BASE,
+ BAST_NOR_SIZE,
+ qemu_ram_alloc(BAST_NOR_SIZE) | IO_MEM_ROM);
+
+ /* initialise board informations */
+ bast_binfo.ram_size = ram_size;
+ bast_binfo.kernel_filename = kernel_filename;
+ bast_binfo.kernel_cmdline = kernel_cmdline;
+ bast_binfo.initrd_filename = initrd_filename;
+ bast_binfo.nb_cpus = 1;
+ bast_binfo.loader_start = BAST_NOR_BASE;
+
+ if (kernel_filename == NULL) {
+ /* No kernel given so try and aquire a bootloader */
+ char buf[PATH_MAX];
+
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+ ret = load_image_targphys(buf, bast_binfo.loader_start, BAST_NOR_SIZE);
+ if (ret <= 0) {
+ perror("qemu");
+ fprintf(stderr, "qemu: warning, could not load BAST BIOS from
%s\n", buf);
+ exit (1);
+ } else {
+ fprintf(stdout, "qemu: info, loaded BAST BIOS %d bytes from %s\n",
ret, buf);
+ }
+ } else {
+ bast_binfo.loader_start = CPU_S3C2410X_RAM;
+ arm_load_kernel(stcb->soc->cpu_env, &bast_binfo);
+ }
+
+ /* Setup initial (reset) program counter */
+ stcb->soc->cpu_env->regs[15] = bast_binfo.loader_start;
+
+ /* Initialise the BAST CPLD */
+ stcb_cpld_register(stcb);
+
+ /* attach i2c devices */
+ stcb_i2c_setup(stcb);
+
+ /* Attach some NAND devices */
+ stcb->nand[0] = NULL;
+ stcb->nand[1] = NULL;
+ index = drive_get_index(IF_MTD, 0, 0);
+ if (index == -1)
+ stcb->nand[2] = NULL;
+ else
+ stcb->nand[2] = nand_init(0xEC, 0x79); /* 128MiB small-page */
+
+ /* And we're good to go */
+}
+
+
+QEMUMachine bast_machine = {
+ .name = "bast",
+ .desc = "Simtec Electronics BAST (S3C2410A, ARM920T)",
+ .init = stcb_init,
+ .max_cpus = 1,
+};
diff -urN qemusvnclean/hw/boards.h qemusvnpatches/hw/boards.h
--- qemusvnclean/hw/boards.h 2009-04-23 14:49:39.000000000 +0100
+++ qemusvnpatches/hw/boards.h 2009-04-23 17:39:07.000000000 +0100
@@ -128,4 +128,10 @@
/* tosa.c */
extern QEMUMachine tosapda_machine;
+/* bast.c */
+extern QEMUMachine bast_machine;
+
+/* smdk2410.c */
+extern QEMUMachine smdk2410_machine;
+
#endif
diff -urN qemusvnclean/hw/smdk2410.c qemusvnpatches/hw/smdk2410.c
--- qemusvnclean/hw/smdk2410.c 1970-01-01 01:00:00.000000000 +0100
+++ qemusvnpatches/hw/smdk2410.c 2009-04-23 17:37:27.000000000 +0100
@@ -0,0 +1,120 @@
+/* hw/smdk2410.c
+ *
+ * System emulation for the Samsung SMDK2410
+ *
+ * Copyright 2006, 2008 Daniel Silverstone and Vincent Sanders
+ *
+ * This file is under the terms of the GNU General Public
+ * License Version 2.
+ */
+
+#include "hw.h"
+#include "sysemu.h"
+#include "arm-misc.h"
+#include "net.h"
+#include "smbus.h"
+#include "flash.h"
+#include "devices.h"
+#include "boards.h"
+
+#include "s3c2410x.h"
+
+#define BIOS_FILENAME "smdk2410.bin"
+
+typedef struct {
+ S3CState *soc;
+ unsigned char cpld_ctrl2;
+ struct nand_flash_s *nand[4];
+} SMDK2410State;
+
+/* Bytes in a Kilobyte */
+#define KILO 1024
+/* Bytes in a megabyte */
+#define MEGA 1024 * KILO
+/* Bytes */
+#define BYTE 1
+/* Bits in a byte */
+#define BIT 8
+
+/* Useful defines */
+#define SMDK2410_NOR_BASE CPU_S3C2410X_CS0
+#define SMDK2410_NOR_SIZE 16 * MEGA / BIT
+#define SMDK2410_BOARD_ID 193
+
+static struct arm_boot_info smdk2410_binfo = {
+ .board_id = SMDK2410_BOARD_ID,
+ .ram_size = 0x10000000, /* 256MB */
+};
+
+static void smdk2410_init(ram_addr_t _ram_size,
+ int vga_ram_size,
+ const char *boot_device,
+ const char *kernel_filename, const char *kernel_cmdline,
+ const char *initrd_filename, const char *cpu_model)
+{
+ SMDK2410State *stcb;
+ int ret, index;
+
+ /* ensure memory is limited to 256MB */
+ if (_ram_size > (256 * MEGA * BYTE))
+ _ram_size = 256 * MEGA * BYTE;
+ ram_size = _ram_size;
+
+ /* allocate storage for board state */
+ stcb = malloc(sizeof(SMDK2410State));
+
+ /* initialise CPU and memory */
+ stcb->soc = s3c2410x_init(ram_size);
+
+ /* Register the NOR flash ROM */
+ cpu_register_physical_memory(SMDK2410_NOR_BASE,
+ SMDK2410_NOR_SIZE,
+ qemu_ram_alloc(SMDK2410_NOR_SIZE) |
IO_MEM_ROM);
+
+ /* initialise board informations */
+ smdk2410_binfo.ram_size = ram_size;
+ smdk2410_binfo.kernel_filename = kernel_filename;
+ smdk2410_binfo.kernel_cmdline = kernel_cmdline;
+ smdk2410_binfo.initrd_filename = initrd_filename;
+ smdk2410_binfo.nb_cpus = 1;
+ smdk2410_binfo.loader_start = SMDK2410_NOR_BASE;
+
+ if (kernel_filename == NULL) {
+ /* No kernel given so try and aquire a bootloader */
+ char buf[PATH_MAX];
+
+ snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
+ ret = load_image_targphys(buf, smdk2410_binfo.loader_start,
SMDK2410_NOR_SIZE);
+ if (ret <= 0) {
+ perror("qemu");
+ fprintf(stderr, "qemu: warning, could not load SMDK2410 BIOS from
%s\n", buf);
+ exit (1);
+ } else {
+ fprintf(stdout, "qemu: info, loaded SMDK2410 BIOS %d bytes from
%s\n", ret, buf);
+ }
+ } else {
+ smdk2410_binfo.loader_start = CPU_S3C2410X_RAM;
+ arm_load_kernel(stcb->soc->cpu_env, &smdk2410_binfo);
+ }
+
+ /* Setup initial (reset) program counter */
+ stcb->soc->cpu_env->regs[15] = smdk2410_binfo.loader_start;
+
+ /* Attach some NAND devices */
+ stcb->nand[0] = NULL;
+ stcb->nand[1] = NULL;
+ index = drive_get_index(IF_MTD, 0, 0);
+ if (index == -1)
+ stcb->nand[2] = NULL;
+ else
+ stcb->nand[2] = nand_init(0xEC, 0x79); /* 128MiB small-page */
+
+}
+
+
+QEMUMachine smdk2410_machine = {
+ .name = "smdk2410",
+ .desc = "Samsung SMDK2410 (S3C2410A, ARM920T)",
+ .init = smdk2410_init,
+ .max_cpus = 1,
+};
diff -urN qemusvnclean/Makefile.target qemusvnpatches/Makefile.target
--- qemusvnclean/Makefile.target 2009-04-23 17:30:24.000000000 +0100
+++ qemusvnpatches/Makefile.target 2009-04-23 17:41:39.000000000 +0100
@@ -665,6 +665,7 @@
OBJS+= s3c24xx_clkcon.o s3c24xx_gpio.o s3c24xx_iic.o
OBJS+= s3c24xx_irq.o s3c24xx_lcd.o s3c24xx_memc.o s3c24xx_nand.o
OBJS+= s3c24xx_rtc.o s3c24xx_serial.o s3c24xx_timers.o
+OBJS+= bast.o smdk2410.o
OBJS+= pflash_cfi01.o gumstix.o
OBJS+= zaurus.o ide.o serial.o nand.o ecc.o spitz.o tosa.o tc6393xb.o
OBJS+= omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o
diff -urN qemusvnclean/target-arm/machine.c qemusvnpatches/target-arm/machine.c
--- qemusvnclean/target-arm/machine.c 2009-04-20 20:26:52.000000000 +0100
+++ qemusvnpatches/target-arm/machine.c 2009-04-23 17:38:07.000000000 +0100
@@ -7,6 +7,8 @@
qemu_register_machine(&versatilepb_machine);
qemu_register_machine(&versatileab_machine);
qemu_register_machine(&realview_machine);
+ qemu_register_machine(&bast_machine);
+ qemu_register_machine(&smdk2410_machine);
qemu_register_machine(&akitapda_machine);
qemu_register_machine(&spitzpda_machine);
qemu_register_machine(&borzoipda_machine);
--
Regards Vincent
http://www.kyllikki.org/
- [Qemu-devel] [PATCH 7/16] S3C serial peripheral, (continued)
- [Qemu-devel] [PATCH 7/16] S3C serial peripheral, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 6/16] S3C Timers, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 8/16] S3C Real Time Clock, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 9/16] S3C General Purpose IO, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 10/16] S3C I2C peripheral, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 11/16] S3C LCD display, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 12/16] S3C NAND controller, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 13/16] S3C2410 SOC implementation, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 14/16] S3C2440 SOC impementation, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 15/16] Add S3C SOC files to Makefile, Vincent Sanders, 2009/04/23
- [Qemu-devel] [PATCH 16/16] Add two boards which use S3C2410 SOC,
Vincent Sanders <=