[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 1/3] r2d add pflash support
From: |
Jean-Christophe PLAGNIOL-VILLARD |
Subject: |
[Qemu-devel] [PATCH 1/3] r2d add pflash support |
Date: |
Sun, 26 Apr 2009 18:36:10 +0200 |
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <address@hidden>
---
Makefile.target | 2 +-
hw/r2d.c | 27 +++++++++++++++++++++------
hw/sh7750_regs.h | 12 ++++++++++++
3 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index ee0f74b..a2e20ec 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -681,7 +681,7 @@ endif
ifeq ($(TARGET_BASE_ARCH), sh4)
OBJS+= shix.o r2d.o sh7750.o sh7750_regnames.o tc58128.o
OBJS+= sh_timer.o sh_serial.o sh_intc.o sh_pci.o sm501.o serial.o
-OBJS+= ide.o
+OBJS+= ide.o pflash_cfi02.o
endif
ifeq ($(TARGET_BASE_ARCH), m68k)
OBJS+= an5206.o mcf5206.o mcf_uart.o mcf_intc.o mcf5208.o mcf_fec.o
diff --git a/hw/r2d.c b/hw/r2d.c
index 950576c..d1a2ccf 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -31,9 +31,11 @@
#include "pci.h"
#include "net.h"
#include "sh7750_regs.h"
+#include "flash.h"
-#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
-#define SDRAM_SIZE 0x04000000
+#define SDRAM_BASE SH7750_A3_BASE /* Physical location of SDRAM: Area 3 */
+#define SDRAM_SIZE 0x04000000
+#define FLASH_SIZE 0x02000000
#define SM501_VRAM_SIZE 0x800000
@@ -204,6 +206,7 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
qemu_irq *irq;
PCIBus *pci;
int i;
+ int index;
if (!cpu_model)
cpu_model = "SH7751R";
@@ -219,10 +222,10 @@ static void r2d_init(ram_addr_t ram_size, int
vga_ram_size,
cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
/* Register peripherals */
s = sh7750_init(env);
- irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
+ irq = r2d_fpga_init(SH7750_A1_BASE, sh7750_irl(s));
pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
- sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
+ sm501_init(SH7750_A4_BASE, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
/* onboard CF (True IDE mode, Master only). */
if ((i = drive_get_index(IF_IDE, 0, 0)) != -1)
@@ -233,6 +236,18 @@ static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
for (i = 0; i < nb_nics; i++)
pci_nic_init(pci, &nd_table[i], (i==0)? 2<<3: -1, "rtl8139");
+ if ((index = drive_get_index(IF_PFLASH, 0, 0)) > -1) {
+ uint32_t sector_len = 128 * 1024;
+
+ if (!pflash_cfi02_register(SH7750_A0_BASE, qemu_ram_alloc(FLASH_SIZE),
+ drives_table[index].bdrv, sector_len, FLASH_SIZE / sector_len,
+ 1, 4, 0, 0, 0, 0, 0, 0)) {
+ fprintf(stderr, "qemu: Error registering flash memory.\n");
+ } else {
+ env->pc = SH7750_P2_BASE;
+ }
+ }
+
/* Todo: register on board registers */
if (kernel_filename) {
int kernel_size;
@@ -244,11 +259,11 @@ static void r2d_init(ram_addr_t ram_size, int
vga_ram_size,
kernel_size = load_image_targphys(kernel_filename,
SDRAM_BASE + LINUX_LOAD_OFFSET,
SDRAM_SIZE - LINUX_LOAD_OFFSET);
- env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
+ env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | SH7750_P2_BASE;
pstrcpy_targphys(SDRAM_BASE + 0x10100, 256, kernel_cmdline);
} else {
kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE,
SDRAM_SIZE);
- env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
+ env->pc = SDRAM_BASE | SH7750_P2_BASE; /* Start from P2 area */
}
if (kernel_size < 0) {
diff --git a/hw/sh7750_regs.h b/hw/sh7750_regs.h
index 5a23a2c..1280fec 100644
--- a/hw/sh7750_regs.h
+++ b/hw/sh7750_regs.h
@@ -23,6 +23,7 @@
* All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
* in 0x1f000000 - 0x1fffffff (area 7 address)
*/
+#define SH7750_P2_BASE 0xa0000000
#define SH7750_P4_BASE 0xff000000 /* Accessable only in
priveleged mode */
#define SH7750_A7_BASE 0x1f000000 /* Accessable only using TLB */
@@ -31,6 +32,17 @@
#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))
/*
+ * External Memory Space
+ */
+#define SH7750_A0_BASE 0x00000000
+#define SH7750_A1_BASE 0x04000000
+#define SH7750_A2_BASE 0x08000000
+#define SH7750_A3_BASE 0x0C000000
+#define SH7750_A4_BASE 0x10000000
+#define SH7750_A5_BASE 0x14000000
+#define SH7750_A6_BASE 0x18000000
+
+/*
* MMU Registers
*/
--
1.6.2.1
- [Qemu-devel] [PATCH 1/3] r2d add pflash support,
Jean-Christophe PLAGNIOL-VILLARD <=