[Qemu-devel] Re: [RFC -v3 1/2] QEMU-KVM: MCE: Add MCE simulation to qemu/tcg

[Huang Ying]

On Sat, 2009-05-09 at 05:08 +0800, Anthony Liguori wrote:
> Huang Ying wrote:
> > - MCE features are initialized when VCPU is intialized according to CPUID.
> > - A monitor command "mce" is added to inject a MCE.
> > - A new interrupt mask: CPU_INTERRUPT_MCE is added to inject the MCE.
> >
> > Signed-off-by: Huang Ying <address@hidden>
> >
> > ---
> >  cpu-all.h               |    4 ++
> >  cpu-exec.c              |    4 ++
> >  monitor.c               |   49 +++++++++++++++++++++++++++++++++
> >  target-i386/cpu.h       |   22 +++++++++++++++
> >  target-i386/helper.c    |   70 
> > ++++++++++++++++++++++++++++++++++++++++++++++++
> >  target-i386/op_helper.c |   34 +++++++++++++++++++++++
> >  6 files changed, 183 insertions(+)
> >
> > --- a/target-i386/cpu.h
> > +++ b/target-i386/cpu.h
> > @@ -202,6 +202,7 @@
> >  #define CR4_DE_MASK   (1 << 3)
> >  #define CR4_PSE_MASK  (1 << 4)
> >  #define CR4_PAE_MASK  (1 << 5)
> > +#define CR4_MCE_MASK  (1 << 6)
> >  #define CR4_PGE_MASK  (1 << 7)
> >  #define CR4_PCE_MASK  (1 << 8)
> >  #define CR4_OSFXSR_SHIFT 9
> > @@ -248,6 +249,17 @@
> >  #define PG_ERROR_RSVD_MASK 0x08
> >  #define PG_ERROR_I_D_MASK  0x10
> >  
> > +#define MCE_CAP_DEF        0x100
> > +#define MCE_BANKS_DEF      4
> > +
> > +#define MCG_CTL_P  (1UL<<8)
> > +
> > +#define MCG_STATUS_MCIP    (1UL<<2)
> > +
> > +#define MCI_STATUS_VAL     (1UL<<63)
> > +#define MCI_STATUS_OVER    (1UL<<62)
> > +#define MCI_STATUS_UC      (1UL<<61)
> > +
> >  #define MSR_IA32_TSC                    0x10
> >  #define MSR_IA32_APICBASE               0x1b
> >  #define MSR_IA32_APICBASE_BSP           (1<<8)
> > @@ -288,6 +300,11 @@
> >  
> >  #define MSR_MTRRdefType                    0x2ff
> >  
> > +#define MSR_MC0_CTL                        0x400
> > +#define MSR_MC0_STATUS                     0x401
> > +#define MSR_MC0_ADDR                       0x402
> > +#define MSR_MC0_MISC                       0x403
> > +
> >  #define MSR_EFER                        0xc0000080
> >  
> >  #define MSR_EFER_SCE   (1 << 0)
> > @@ -674,6 +691,11 @@ typedef struct CPUX86State {
> >         user */
> >      struct APICState *apic_state;
> >      uint32_t mp_state;
> > +
> > +    uint64 mcg_cap;
> > +    uint64 mcg_status;
> > +    uint64 mcg_ctl;
> > +    uint64 *mce_banks;
> >  } CPUX86State;
> >
> >   
> 
> Doesn't this need to be added to the savevm/loadvm state?

Yes. I will add it.

Best Regards,
Huang Ying

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