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[Qemu-devel] [PATCH] q35 chipset based pc. wip.
|
From: |
Isaku Yamahata |
|
Subject: |
[Qemu-devel] [PATCH] q35 chipset based pc. wip. |
|
Date: |
Thu, 18 Jun 2009 20:00:58 +0900 |
|
User-agent: |
Mutt/1.5.6i |
This patch is under work in progres as it I haven't successed to boot yet.
This patch is sent out to show the intention of the series of patches.
Signed-off-by: Isaku Yamahata <address@hidden>
--
Makefile.target | 1
hw/acpi_ich9.c | 542 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/acpi_ich9.h | 53 +++++
hw/pc_q35.c | 199 ++++++++++++++++++
hw/pci.h | 60 +++++
hw/pci_ids.h | 25 ++
hw/q35.c | 587 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/q35.h | 213 ++++++++++++++++++++
hw/q35_smbus.c | 177 ++++++++++++++++
9 files changed, 1850 insertions(+), 7 deletions(-)
diff --git a/Makefile.target b/Makefile.target
index 4d0d01f..722c818 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -574,6 +574,7 @@ OBJS+= ide.o pckbd.o vga.o $(SOUND_HW) dma.o
OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
OBJS+= cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o
OBJS+= pc_piix.o acpi_piix4.o pc_smbus.o pc_apm.o
+OBJS+= pc_q35.o q35.o q35_smbus.o acpi_ich9.o
OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
OBJS += device-hotplug.o pci-hotplug.o smbios.o
CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
new file mode 100644
index 0000000..83642f8
--- /dev/null
+++ b/hw/acpi_ich9.c
@@ -0,0 +1,542 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "acpi.h"
+
+#include "q35.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define ICH9_DEBUG(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
+#else
+#define ICH9_DEBUG(fmt, ...) do { } while (0)
+#endif
+
+/* XXX where does the constant, ACPI_DBG_IO_ADDR, come from */
+#define ACPI_DBG_IO_ADDR 0xb044
+static void acpi_dbg_writel(void *opaqe, uint32_t addr, uint32_t val)
+{
+ ICH9_DEBUG("%s: 0x%08x\n", __func__, val);
+}
+
+void acpi_dbg_init(void); /* XXX */
+void acpi_dbg_init(void)
+{
+ register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, NULL);
+}
+
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val);
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
+static void gpe_ioport_writeb(struct ich9_lpc_pm_regs *pm,
+ uint32_t addr, uint32_t val);
+static uint32_t gpe_ioport_readb(struct ich9_lpc_pm_regs *pm,
+ uint32_t addr);
+
+#define ACPI_ENABLE 0x2
+#define ACPI_DISABLE 0x3
+
+static struct ich9_lpc_pm_regs *pm_state;
+
+static uint32_t get_pmtmr(struct ich9_lpc_pm_regs *pm)
+{
+ uint32_t d;
+ d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, ticks_per_sec);
+ return d & 0xffffff;
+}
+
+static int get_pm1_sts(struct ich9_lpc_pm_regs *pm)
+{
+ int64_t d;
+ int pm1_sts;
+ pm1_sts = pm->pm1_sts;
+ d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY, ticks_per_sec);
+ if (d >= pm->tmr_overflow_time)
+ pm->pm1_sts |= ACPI_BITMASK_TIMER_STATUS;
+ return pm->pm1_sts;
+}
+
+static void pm_update_sci(struct ich9_lpc_pm_regs *pm)
+{
+ int sci_level, pm1_sts;
+ int64_t expire_time;
+
+ pm1_sts = get_pm1_sts(pm);
+ sci_level = (((pm1_sts & pm->pm1_en) &
+ (ACPI_BITMASK_RT_CLOCK_ENABLE |
+ ACPI_BITMASK_POWER_BUTTON_ENABLE |
+ ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
+ ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ qemu_set_irq(pm->irq, sci_level);
+ /* schedule a timer interruption if needed */
+ if ((pm->pm1_en & ACPI_BITMASK_TIMER_ENABLE) &&
+ !(pm1_sts & ACPI_BITMASK_TIMER_STATUS)) {
+ expire_time = muldiv64(pm->tmr_overflow_time, ticks_per_sec,
+ PM_TIMER_FREQUENCY);
+ qemu_mod_timer(pm->tmr_timer, expire_time);
+ } else {
+ qemu_del_timer(pm->tmr_timer);
+ }
+}
+
+static void pm_tmr_timer(void *opaque)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+ pm_update_sci(pm);
+}
+
+static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+
+ addr &= ICH9_PMIO_MASK;
+ switch (addr) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + 7):
+ case ICH9_PMIO_GPE0_EN ... (ICH9_PMIO_GPE0_EN + 7):
+ gpe_ioport_writeb(pm, addr, val);
+ break;
+ default:
+ break;
+ }
+
+ ICH9_DEBUG("%s port=0x%04x val=0x%04x\n", __func__, addr, val);
+
+}
+
+static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+ uint32_t val = 0;
+
+ addr &= ICH9_PMIO_MASK;
+ switch(addr) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + 7):
+ case ICH9_PMIO_GPE0_EN ... (ICH9_PMIO_GPE0_EN + 7):
+ val = gpe_ioport_readb(pm, addr);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ ICH9_DEBUG("%s port=0x%04x val=0x%04x\n", __func__, addr, val);
+ return val;
+}
+
+static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+
+ addr &= ICH9_PMIO_MASK;
+ switch(addr) {
+ case ICH9_PMIO_PM1_STS:
+ {
+ int64_t d;
+ int pm1_sts;
+ pm1_sts = get_pm1_sts(pm);
+ if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) {
+ /* if TMRSTS is reset, then compute the new overflow time */
+ d = muldiv64(qemu_get_clock(vm_clock), PM_TIMER_FREQUENCY,
+ ticks_per_sec);
+ pm->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
+ }
+ pm->pm1_sts &= ~val;
+ pm_update_sci(pm);
+ }
+ break;
+ case ICH9_PMIO_PM1_EN:
+ pm->pm1_en = val;
+ pm_update_sci(pm);
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ {
+ int sus_typ;
+ pm->pm1_cnt = val & ~(ACPI_BITMASK_SLEEP_ENABLE);
+ if (val & ACPI_BITMASK_SLEEP_ENABLE) {
+ /* change suspend type */
+ sus_typ = (val >> 10) & 7;
+ switch(sus_typ) {
+ case 0: /* soft power off */
+ qemu_system_shutdown_request();
+ break;
+ case 1:
+ /* ACPI_BITMASK_WAKE_STATUS should be set on resume.
+ Pretend that resume was caused by power button */
+ pm->pm1_sts |= (ACPI_BITMASK_WAKE_STATUS |
+ ACPI_BITMASK_POWER_BUTTON_STATUS);
+ qemu_system_reset_request();
+#if defined(TARGET_I386)
+ cmos_set_s3_resume();
+#endif
+ default:
+ break;
+ }
+ }
+ }
+ break;
+ default:
+ pm_ioport_write_fallback(opaque, addr, 2, val);
+ break;
+ }
+ ICH9_DEBUG("%s port=0x%04x val=0x%04x\n", __func__, addr, val);
+}
+
+static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+ uint32_t val;
+
+ addr &= ICH9_PMIO_MASK;
+ switch(addr) {
+ case ICH9_PMIO_PM1_STS:
+ val = get_pm1_sts(pm);
+ break;
+ case ICH9_PMIO_PM1_EN:
+ val = pm->pm1_en;
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ val = pm->pm1_cnt;
+ break;
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 2);
+ break;
+ }
+ ICH9_DEBUG("%s port=0x%04x val=0x%04x\n", __func__, addr, val);
+ return val;
+}
+
+static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
+{
+ // struct ich9_lpc_pm_regs *pm = opaque;
+
+ addr &= ICH9_PMIO_MASK;
+ switch(addr) {
+ default:
+ pm_ioport_write_fallback(opaque, addr, 4, val);
+ break;
+ }
+ ICH9_DEBUG("%s port=0x%04x val=0x%08x\n", __func__, addr, val);
+}
+
+static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
+{
+ struct ich9_lpc_pm_regs *pm = opaque;
+ uint32_t val;
+
+ addr &= ICH9_PMIO_MASK;
+ switch(addr) {
+ case ICH9_PMIO_PM1_TMR:
+ val = get_pmtmr(pm);
+ break;
+
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 4);
+ break;
+ }
+ ICH9_DEBUG("%s port=0x%04x val=0x%08x\n", __func__, addr, val);
+ return val;
+}
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val)
+{
+ int subsize = (len == 4)? 2: 1;
+ IOPortWriteFunc *ioport_write =
+ (subsize == 2)? pm_ioport_writew: pm_ioport_writeb;
+
+ int i;
+
+ for (i = 0; i < len; i += subsize) {
+ ioport_write(opaque, addr, val);
+ val >>= 8 * subsize;
+ }
+}
+
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
+{
+ int subsize = (len == 4)? 2: 1;
+ IOPortReadFunc *ioport_read =
+ (subsize == 2)? pm_ioport_readw: pm_ioport_readb;
+
+ uint32_t val;
+ int i;
+
+ val = 0;
+ for (i = 0; i < len; i += subsize) {
+ val <<= 8 * subsize;
+ val |= ioport_read(opaque, addr);
+ }
+
+ return val;
+}
+
+void ich9_pm_iospace_update(struct ich9_lpc_pm_regs *pm, uint32_t pm_io_base)
+{
+ /* XXX: need to improve memory and ioport allocation */
+ ICH9_DEBUG("%s to 0x%x\n", __func__, pm_io_base);
+
+ assert((pm_io_base & ~ICH9_PMIO_MASK) == 0);
+
+ if (pm->pm_io_base != 0)
+ isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
+
+ /* XXX: tmp hack */
+ if (pm_io_base == 0)
+ return;
+
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
+
+ pm->pm_io_base = pm_io_base;
+}
+
+void ich9_pm_save(QEMUFile* f, struct ich9_lpc_pm_regs *pm)
+{
+ qemu_put_be16s(f, &pm->pm1_sts);
+ qemu_put_be16s(f, &pm->pm1_en);
+ qemu_put_be16s(f, &pm->pm1_cnt);
+ qemu_put_timer(f, pm->tmr_timer);
+ qemu_put_be64(f, pm->tmr_overflow_time);
+ qemu_put_be64s(f, &pm->gpe0_sts);
+ qemu_put_be64s(f, &pm->gpe0_en);
+ qemu_put_be32s(f, &pm->smi_en);
+ qemu_put_be32s(f, &pm->smi_sts);
+}
+
+void ich9_pm_load(QEMUFile* f, struct ich9_lpc_pm_regs *pm, int version_id)
+{
+ qemu_get_be16s(f, &pm->pm1_sts);
+ qemu_get_be16s(f, &pm->pm1_en);
+ qemu_get_be16s(f, &pm->pm1_cnt);
+ qemu_get_timer(f, pm->tmr_timer);
+ pm->tmr_overflow_time = qemu_get_be64(f);
+ qemu_get_be64s(f, &pm->gpe0_sts);
+ qemu_get_be64s(f, &pm->gpe0_en);
+ qemu_get_be32s(f, &pm->smi_en);
+ qemu_get_be32s(f, &pm->smi_sts);
+}
+
+static void pm_reset(void *opaque)
+{
+ //struct ich9_lpc_pm_regs *pm = opaque;
+ /* XXX:TODO */
+}
+
+#if defined(TARGET_I386)
+static void pm_powerdown(void *arg)
+{
+ struct ich9_lpc_pm_regs *pm = (struct ich9_lpc_pm_regs*) arg;
+
+ if (pm->pm1_en & ACPI_BITMASK_POWER_BUTTON_ENABLE) {
+ pm->pm1_sts |= ACPI_BITMASK_POWER_BUTTON_STATUS;
+ pm_update_sci(pm);
+ }
+}
+#endif
+
+void ich9_pm_init(struct ich9_lpc_pm_regs *pm, qemu_irq sci_irq)
+{
+ pm->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, pm);
+
+ pm->irq = sci_irq;
+ qemu_register_reset(pm_reset, 0, pm);
+ qemu_system_powerdown_register(pm_powerdown, pm_state);
+}
+
+/* GPE */
+static uint8_t *gpe_ioport_get_ptr(struct ich9_lpc_pm_regs *pm, uint32_t addr)
+{
+ uint8_t *cur = NULL;
+
+ switch (addr) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + 7):
+ cur = (uint8_t*)&pm->gpe0_sts;
+ cur += addr - ICH9_PMIO_GPE0_STS;
+ break;
+ case ICH9_PMIO_GPE0_EN ... (ICH9_PMIO_GPE0_EN + 7):
+ cur = (uint8_t*)&pm->gpe0_en;
+ cur += addr - ICH9_PMIO_GPE0_EN;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ return cur;
+}
+
+static void gpe_ioport_writeb(struct ich9_lpc_pm_regs *pm,
+ uint32_t addr, uint32_t val)
+{
+ uint8_t *cur = gpe_ioport_get_ptr(pm, addr);
+
+ val &= 0xff;
+ switch (addr) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + 7):
+ *cur = (*cur) & ~val;
+ break;
+ case ICH9_PMIO_GPE0_EN ... (ICH9_PMIO_GPE0_EN + 7):
+ *cur = val;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ ICH9_DEBUG("%s %x <== %d\n", __func__, addr, val);
+}
+
+static uint32_t gpe_ioport_readb(struct ich9_lpc_pm_regs *pm,
+ uint32_t addr)
+{
+ uint8_t *cur = gpe_ioport_get_ptr(pm, addr);
+ uint32_t val = 0;
+
+ if (cur != NULL)
+ val = *cur;
+
+ ICH9_DEBUG("%s %x == %x\n", __func__, addr, val);
+ return val;
+}
+
+#if 0
+/* XXX TODO */
+#define PCI_BASE 0xae00
+#define PCI_EJ_BASE 0xae08
+
+struct pci_status {
+ uint32_t up;
+ uint32_t down;
+};
+
+static struct pci_status pci0_status;
+
+
+static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ val = g->up;
+ break;
+ case PCI_BASE + 4:
+ val = g->down;
+ break;
+ default:
+ break;
+ }
+
+ ICH9_DEBUG("%s %x == %x\n", __func__, addr, val);
+ return val;
+}
+
+static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ struct pci_status *g = opaque;
+ switch (addr) {
+ case PCI_BASE:
+ g->up = val;
+ break;
+ case PCI_BASE + 4:
+ g->down = val;
+ break;
+ }
+
+ ICH9_DEBUG("%s %x <== %d\n", __func__, addr, val);
+}
+
+static uint32_t pciej_read(void *opaque, uint32_t addr)
+{
+ ICH9_DEBUG("%s %x\n", __func__, addr);
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+#if defined (TARGET_I386)
+ int slot = ffs(val) - 1;
+
+ pci_device_hot_remove_success(0, slot);
+#endif
+
+ ICH9_DEBUG("%s %x <== %d\n", __func__, addr, val);
+}
+
+
+void ich9_hot_add_init(void)
+{
+ register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
+ register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
+}
+
+static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ p->up |= (1 << slot);
+}
+
+static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
+{
+ g->sts |= 2;
+ p->down |= (1 << slot);
+}
+
+void qemu_system_device_hot_add(int bus, int slot, int state)
+{
+ pci0_status.up = 0;
+ pci0_status.down = 0;
+ if (state)
+ enable_device(&pci0_status, &gpe, slot);
+ else
+ disable_device(&pci0_status, &gpe, slot);
+ if (gpe.en & 2) {
+ qemu_set_irq(pm_state->irq, 1);
+ qemu_set_irq(pm_state->irq, 0);
+ }
+}
+#else
+static void ich9_device_hot_add(int bus, int slot, int state)
+{
+ /* stub */
+}
+
+void ich9_hot_add_init(void)
+{
+ /* stub */
+
+ qemu_system_device_hot_add_register(ich9_device_hot_add);
+}
+#endif
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
new file mode 100644
index 0000000..57a4bfe
--- /dev/null
+++ b/hw/acpi_ich9.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU GMCH/ICH9 LPC PM Emulation
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ */
+
+#ifndef HW_ACPI_ICH9_H
+#define HW_ACPI_ICH9_H
+
+#include <stdint.h>
+
+struct ich9_lpc_pm_regs {
+ uint16_t pm1_sts;
+ uint16_t pm1_en;
+
+ /*
+ * In ich9 spec says that pm1_cnt register is 32bit width and
+ * that the upper 16bits are reserved and unused.
+ * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
+ */
+ uint16_t pm1_cnt;
+
+ /* uint32_t pm1_tmr; */
+ QEMUTimer *tmr_timer;
+ int64_t tmr_overflow_time;
+
+ uint64_t gpe0_sts;
+ uint64_t gpe0_en;
+
+ uint32_t smi_en;
+ uint32_t smi_sts;
+
+ qemu_irq irq; /* SCI */
+
+ uint32_t pm_io_base;
+};
+
+#endif /* HW_ACPI_ICH9_H */
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 0000000..ae539e1
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,199 @@
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ */
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "block.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"
+
+#include "q35.h"
+
+#define MAX_IDE_BUS 2
+
+static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
+static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
+static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
+
+/* PC hardware initialisation */
+static void pc_q35_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
+{
+ int i;
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+ PCIBus *host_bus;
+ PCIBus *pci_bus;
+ static PCIDevice *gmch_state;
+ int ich9_lpc_devfn = -1;
+ qemu_irq *cpu_irq;
+ qemu_irq *i8259;
+ int index;
+ BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ IOAPICState *ioapic;
+ fdctrl_t *floppy_controller;
+ RTCState *rtc_state;
+
+ pc_cpus_init(cpu_model);
+
+ vmport_init();
+
+ /* allocate ram and load rom/bios */
+ pc_memory_init(ram_size, kernel_filename, kernel_cmdline, initrd_filename,
+ &below_4g_mem_size, &above_4g_mem_size);
+
+
+ cpu_irq = pc_allocte_cpu_irq();
+ i8259 = i8259_init(cpu_irq[0]);
+ pc_register_ferr_irq(i8259[13]);
+
+ host_bus = gmch_init(&gmch_state, i8259);
+ ich9_lpc_devfn = ich9_lpc_init(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
+ ICH9_LPC_FUNC), i8259);
+ pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
+ ICH9_D2P_BRIDGE_FUNC),
+ ICH9_D2P_SECONDARY_DEFAULT);
+
+ pc_vga_init(pci_bus);
+
+ /* init basic PC hardware */
+ pc_basic_device_init(i8259, &floppy_controller, &rtc_state);
+
+ ioapic = ioapic_init();
+ pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
+
+#if 0
+ if (pci_device_init() < 0) {
+ exit(1);
+ }
+#endif
+
+ watchdog_pc_init(pci_bus);
+
+ for(i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ pci_nic_init(pci_bus, nd, -1, "ne2k_pci");
+ }
+
+ ich9_hot_add_init(); /* XXX */
+
+ if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
+ fprintf(stderr, "qemu: too many IDE bus\n");
+ exit(1);
+ }
+
+ for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
+ index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
+ if (index != -1)
+ hd[i] = drives_table[index].bdrv;
+ else
+ hd[i] = NULL;
+ }
+
+ /* XXX ich9 supports only SATA */
+ pci_piix3_ide_init(host_bus, hd, -1, i8259);
+
+#ifdef HAS_AUDIO
+ audio_init(pci_bus, i8259);
+#endif
+
+ pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd,
+ floppy_controller, rtc_state);
+
+ if (usb_enabled) {
+ /* XXX: make ich9 specific add usb_uchi_ich9_init() */
+ usb_uhci_piix4_init(host_bus, -1);
+ }
+
+ if (acpi_enabled) {
+ uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this
persistent */
+ i2c_bus *smbus;
+
+ /* TODO: Populate SPD eeprom data. */
+ /* XXX determine proper smb_io_base */
+ smbus = ich9_smb_init(pci_bus, ich9_lpc_devfn + 3, 0xb100);
+ for (i = 0; i < 8; i++) {
+ DeviceState *eeprom;
+ eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
+ qdev_set_prop_int(eeprom, "address", 0x50 + i);
+ qdev_set_prop_ptr(eeprom, "data", eeprom_buf + (i * 256));
+ qdev_init(eeprom);
+ }
+ }
+
+ if (gmch_state) {
+ gmch_init_memory_mappings(gmch_state);
+ }
+
+ pc_pci_device_init(pci_bus);
+}
+
+static QEMUMachine pc_q35_machine = {
+ .name = "pc_q35",
+ .desc = "Q35 chipset PC",
+ .init = pc_q35_init,
+ .max_cpus = 255,
+};
+
+static void pc_q35_machine_init(void)
+{
+ qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);
diff --git a/hw/pci.h b/hw/pci.h
index c14ab0f..6c6ddc3 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -161,11 +161,21 @@ typedef struct PCIIORegion {
/* Bits in the PCI Status Register (PCI 2.3 spec) */
#define PCI_STATUS_RESERVED1 0x007
#define PCI_STATUS_INT_STATUS 0x008
-#define PCI_STATUS_CAPABILITIES 0x010
-#define PCI_STATUS_66MHZ 0x020
-#define PCI_STATUS_RESERVED2 0x040
-#define PCI_STATUS_FAST_BACK 0x080
+#define PCI_STATUS_CAPABILITIES 0x10 /* Support Capability List */
+#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
+#define PCI_STATUS_UDF 0x40 /* Support User Definable Features
[obsolete] */
+#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
+#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL 0x600
+#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
+#define PCI_STATUS_DEVSEL_FAST 0x000
+#define PCI_STATUS_DEVSEL_MEDIUM 0x200
+#define PCI_STATUS_DEVSEL_SLOW 0x400
+#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
+#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
+#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
+#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
+#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
#define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
@@ -347,22 +357,58 @@ int pci_assign_devaddr(const char *addr, int *domp, int
*busp, unsigned *slotp);
void pci_info(Monitor *mon);
+static inline uint8_t
+pci_config_get8(uint8_t *pci_config, uint32_t addr)
+{
+ return pci_config[addr];
+}
+
+static inline uint16_t
+pci_config_get16(uint8_t *pci_config, uint32_t addr)
+{
+ return le16_to_cpup((uint16_t *)&pci_config[addr]);
+}
+
+static inline uint32_t
+pci_config_get32(uint8_t *pci_config, uint32_t addr)
+{
+ return le32_to_cpup((uint32_t *)&pci_config[addr]);
+}
+
+static inline void
+pci_config_set8(uint8_t *pci_config, uint32_t addr, uint8_t val)
+{
+ pci_config[addr] = val;
+}
+
+static inline void
+pci_config_set16(uint8_t *pci_config, uint32_t addr, uint16_t val)
+{
+ cpu_to_le16wu((uint16_t *)&pci_config[addr], val);
+}
+
+static inline void
+pci_config_set32(uint8_t *pci_config, uint32_t addr, uint32_t val)
+{
+ cpu_to_le32wu((uint32_t *)&pci_config[addr], val);
+}
+
static inline void
pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
{
- cpu_to_le16wu((uint16_t *)&pci_config[PCI_VENDOR_ID], val);
+ pci_config_set16(pci_config, PCI_VENDOR_ID, val);
}
static inline void
pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
{
- cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
+ pci_config_set16(pci_config, PCI_DEVICE_ID, val);
}
static inline void
pci_config_set_class(uint8_t *pci_config, uint16_t val)
{
- cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
+ pci_config_set16(pci_config, PCI_CLASS_DEVICE, val);
}
typedef void (*pci_qdev_initfn)(PCIDevice *dev);
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index f7d0387..4eb6d07 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -33,6 +33,7 @@
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_PCI 0x0604
+#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
@@ -40,6 +41,18 @@
#define PCI_CLASS_PROCESSOR_CO 0x0b40
#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
+#define PCI_BASE_CLASS_SERIAL 0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE 0x0c00
+#define PCI_CLASS_SERIAL_FIREWIRE_OHCI 0x0c0010
+#define PCI_CLASS_SERIAL_ACCESS 0x0c01
+#define PCI_CLASS_SERIAL_SSA 0x0c02
+#define PCI_CLASS_SERIAL_USB 0x0c03
+#define PCI_CLASS_SERIAL_USB_UHCI 0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI 0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI 0x0c0320
+#define PCI_CLASS_SERIAL_FIBER 0x0c04
+#define PCI_CLASS_SERIAL_SMBUS 0x0c05
+
#define PCI_CLASS_OTHERS 0xff
/* Vendors and devices. Sort key: vendor first, device next. */
@@ -97,4 +110,16 @@
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
+#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
+
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+
#define PCI_VENDOR_ID_INVALID 0xffff
diff --git a/hw/q35.c b/hw/q35.c
new file mode 100644
index 0000000..beea981
--- /dev/null
+++ b/hw/q35.c
@@ -0,0 +1,587 @@
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on piix_pci.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ */
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw.h"
+#include "pc.h"
+#include "pc_apm.h"
+#include "pci.h"
+#include "q35.h"
+
+typedef uint32_t pci_addr_t;
+#include "pci_host.h"
+
+typedef struct GMCHState {
+ PCIHostState host;
+
+ struct PCIDevice *dev;
+} GMCHState;
+
+struct GMCH_PCIDevice {
+ PCIDevice d;
+ GMCHState *gmch;
+
+ target_phys_addr_t isa_page_descs[384 / 4];
+ uint8_t smm_enabled;
+};
+
+static void gmch_addr_writel(void* opaque, uint32_t addr, uint32_t val)
+{
+ GMCHState *s = opaque;
+ s->host.config_reg = val;
+}
+
+static uint32_t gmch_addr_readl(void* opaque, uint32_t addr)
+{
+ GMCHState *s = opaque;
+ return s->host.config_reg;
+}
+
+static void ich9_lpc_set_irq(qemu_irq *pic, int irq_num, int level);
+
+/* return the global irq number corresponding to a given device irq
+ pin. We could also use the bus number to have a more precise
+ mapping. */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+{
+ int slot_addend;
+ slot_addend = (pci_dev->devfn >> 3) - 1;
+ return (irq_num + slot_addend) & 3;
+}
+
+static target_phys_addr_t isa_page_descs[384 / 4];
+
+static target_phys_addr_t isa_page_descs_get(uint32_t addr)
+{
+ return isa_page_descs[
+ (addr - Q35_HOST_BRIDGE_SMARM_C_BASE) >> TARGET_PAGE_BITS];
+}
+
+static void update_pam(PCIDevice *d, uint32_t start, uint8_t r)
+{
+ uint32_t addr;
+
+ // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
+ switch(r) {
+ case Q35_HOST_BRIDGE_PAM_WE | Q35_HOST_BRIDGE_PAM_RE:
+ /* RAM */
+ cpu_register_physical_memory(start, Q35_HOST_BRIDGE_PAM_AREA_SIZE,
+ start);
+ break;
+
+ case Q35_HOST_BRIDGE_PAM_RE:
+ /* ROM (XXX: not quite correct) */
+ cpu_register_physical_memory(start, Q35_HOST_BRIDGE_PAM_AREA_SIZE,
+ start | IO_MEM_ROM);
+ break;
+
+ case Q35_HOST_BRIDGE_PAM_WE:
+ case 0:
+ /* XXX: should distinguish read/write cases */
+ for(addr = start; addr < start + Q35_HOST_BRIDGE_PAM_AREA_SIZE;
+ addr += TARGET_PAGE_SIZE) {
+ cpu_register_physical_memory(addr, TARGET_PAGE_SIZE,
+ isa_page_descs_get(addr));
+ }
+ break;
+
+ default:
+ assert(0);
+ break;
+ }
+}
+
+static uint8_t gmch_get_pam_attr(PCIDevice *d, uint32_t addr, int hi)
+{
+ return (d->config[addr] >> ((!!hi) * 4)) & Q35_HOST_BRIDGE_PAM_MASK;
+}
+
+static void gmch_update_pam(PCIDevice *d, int pam)
+{
+ uint32_t conf_addr = Q35_HOST_BRIDGE_PAM0 + pam;
+ uint32_t phys_addr;
+
+ assert(0 <= pam && pam <= 6);
+
+ if (pam == 0) {
+ update_pam(d, Q35_HOST_BRIDGE_PAM_BIOS_AREA,
+ gmch_get_pam_attr(d, conf_addr, 1));
+ return;
+ }
+
+ phys_addr = Q35_HOST_BRIDGE_PAM_EXPAN_AREA +
+ Q35_HOST_BRIDGE_PAM_EXPAN_AREA * (pam - 1) * 2;
+ update_pam(d, phys_addr, gmch_get_pam_attr(d, conf_addr, 0));
+
+ phys_addr += Q35_HOST_BRIDGE_PAM_AREA_SIZE;
+ update_pam(d, phys_addr, gmch_get_pam_attr(d, conf_addr, 1));
+}
+
+static void gmch_update_memory_mappings(PCIDevice *d)
+{
+ int i;
+
+ for (i = 0; i < 7; i++)
+ gmch_update_pam(d, i);
+}
+
+static void gmch_update_smram(PCIDevice *d)
+{
+ struct GMCH_PCIDevice *gd = (struct GMCH_PCIDevice*)d;
+ uint32_t smram;
+ uint32_t addr;
+
+ smram = d->config[Q35_HOST_BRDIGE_SMRAM];
+ if ((gd->smm_enabled && (smram & Q35_HOST_BRIDGE_SMRAM_G_SMRAME)) ||
+ (smram & Q35_HOST_BRIDGE_SMRAM_D_OPEN)) {
+ cpu_register_physical_memory(Q35_HOST_BRIDGE_SMARM_C_BASE,
+ Q35_HOST_BRIDGE_SMRAM_C_SIZE,
+ Q35_HOST_BRIDGE_SMARM_C_BASE);
+ } else {
+ for(addr = Q35_HOST_BRIDGE_SMARM_C_BASE;
+ addr < Q35_HOST_BRIDGE_SMRAM_C_END;
+ addr += TARGET_PAGE_SIZE) {
+ cpu_register_physical_memory(addr, TARGET_PAGE_SIZE,
+ isa_page_descs_get(addr));
+ }
+ }
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+ uint8_t val = (smm != 0);
+ struct GMCH_PCIDevice *gd = (struct GMCH_PCIDevice*)arg;
+
+ if (gd->smm_enabled != val) {
+ gd->smm_enabled = val;
+ gmch_update_smram(&gd->d);
+ }
+}
+
+/* XXX: suppress when better memory API. We make the assumption that
+ no device (in particular the VGA) changes the memory mappings in
+ the 0xa0000-0x100000 =
+ [Q35_HOST_BRIDGE_SMARM_C_BASE, Q35_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END)
+ range */
+void gmch_init_memory_mappings(PCIDevice *d)
+{
+ int i;
+ for(i = 0; i < 96; i++) {
+ isa_page_descs[i] =
cpu_get_physical_page_desc(Q35_HOST_BRIDGE_SMARM_C_BASE + i * 0x1000);
+ }
+}
+
+static void gmch_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ /* XXX: implement SMRAM.D_LOCK */
+ pci_default_write_config(d, address, val, len);
+ if ((address >= 0x59 && address <= 0x5f))
+ gmch_update_memory_mappings(d);
+
+ if (address <= Q35_HOST_BRDIGE_SMRAM &&
+ Q35_HOST_BRDIGE_SMRAM <= address + len)
+ gmch_update_smram(d);
+}
+
+static void gmch_save(QEMUFile* f, void *opaque)
+{
+ struct GMCH_PCIDevice *gd = opaque;
+
+ pci_device_save(&gd->d, f);
+ qemu_put_8s(f, &gd->smm_enabled);
+}
+
+static int gmch_load(QEMUFile* f, void *opaque, int version_id)
+{
+ struct GMCH_PCIDevice *gd = opaque;
+ int ret;
+
+ if (version_id > 2)
+ return -EINVAL;
+
+ ret = pci_device_load(&gd->d, f);
+ if (ret < 0)
+ return ret;
+ gmch_update_memory_mappings(&gd->d);
+
+ qemu_get_8s(f, &gd->smm_enabled);
+ gmch_update_smram(&gd->d);
+
+ return 0;
+}
+
+/* host bridge */
+PCIBus *gmch_init(PCIDevice **pgmch_state, qemu_irq *pic)
+{
+ PCIBus *b;
+ PCIDevice *d;
+ struct GMCH_PCIDevice *gd;
+ GMCHState *s;
+
+ s = qemu_mallocz(sizeof(GMCHState));
+ b = pci_register_bus(NULL, "pci",
+ ich9_lpc_set_irq, pci_slot_get_pirq, pic, 0,
+ 8 /* PIRQ A-H */);
+ s->host.bus = b;
+
+ register_ioport_write(Q35_HOST_BRIDGE_CONFIG_ADDR,
+ 4, 4, gmch_addr_writel, s);
+ register_ioport_read(Q35_HOST_BRIDGE_CONFIG_ADDR,
+ 4, 4, gmch_addr_readl, s);
+
+ register_ioport_write(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 1, pci_host_data_writeb, s);
+ register_ioport_write(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 2, pci_host_data_writew, s);
+ register_ioport_write(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 4, pci_host_data_writel, s);
+ register_ioport_read(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 1, pci_host_data_readb, s);
+ register_ioport_read(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 2, pci_host_data_readw, s);
+ register_ioport_read(Q35_HOST_BRIDGE_CONFIG_DATA,
+ 4, 4, pci_host_data_readl, s);
+
+ d = pci_register_device(b, Q35_HOST_BRIDGE,
+ sizeof(struct GMCH_PCIDevice), 0,
+ NULL, gmch_write_config);
+ s->dev = d;
+ gd = (struct GMCH_PCIDevice*)d;
+ gd->gmch = s;
+
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
+ d->config[PCI_REVISION_ID] = Q35_HOST_BRIDGE_REVISION_DEFUALT;
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+ d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
+
+ d->config[Q35_HOST_BRDIGE_SMRAM] = Q35_HOST_BRIDGE_SMRAM_DEFAULT;
+
+ register_savevm(Q35_HOST_BRIDGE, 0, 2, gmch_save, gmch_load, gd);
+ cpu_smm_register(&gmch_set_smm, gd);
+
+ *pgmch_state = d;
+ return b;
+}
+
+/* ICH9 DMI-to-PCI bridge */
+static int ich9_d2pbr_map_irq_fn(PCIDevice *pci_dev, int irq_num)
+{
+ return irq_num;
+}
+
+static void ich9_d2pbr_reset(PCIDevice *d)
+{
+ uint8_t *pci_conf = d->config;
+
+ pci_config_set16(pci_conf, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ pci_config_set16(pci_conf, PCI_STATUS,
+ PCI_STATUS_DEVSEL_MEDIUM);
+}
+
+static void ich9_d2pbr_save(QEMUFile* f, void *opaque)
+{
+ PCIDevice *d = opaque;
+ pci_device_save(d, f);
+}
+
+static int ich9_d2pbr_load(QEMUFile* f, void *opaque, int version_id)
+{
+ PCIDevice *d = opaque;
+ if (version_id != 2)
+ return -EINVAL;
+ return pci_device_load(d, f);
+}
+
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int secondary_bus_num)
+{
+ PCIBus *b;
+ PCIDevice *d;
+ uint8_t *pci_conf;
+
+ b = pci_bridge_create_simple(bus, devfn,
+ PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0,
+ ich9_d2pbr_map_irq_fn, ICH9_D2P_BRIDGE,
+ secondary_bus_num);
+ if (b == NULL)
+ return NULL;
+
+ d = pci_bus_to_dev(b);
+ register_savevm(ICH9_D2P_BRIDGE, 0, ICH9_D2P_BRIDGE_SAVEVM_VERSION,
+ ich9_d2pbr_save, ich9_d2pbr_load, d);
+
+ /* some command bits are hotwired to 0 for pcie */
+ pci_conf_initw(d, PCI_COMMAND, d->callback[PCI_COMMAND],
+ PCI_COMMAND_IO |
+ PCI_COMMAND_MEMORY |
+ PCI_COMMAND_MASTER |
+ PCI_COMMAND_PARITY |
+ PCI_COMMAND_SERR);
+
+ pci_conf = d->config;
+
+ pci_config_set8(pci_conf, PCI_REVISION_ID, ICH9_D2P_A2_REVISION);
+
+ // XXX
+ pci_config_set8(pci_conf, PCI_CLASS_INTERFACE,
+ PCI_CLASS_BRDIGE_PCI_INF_SUB);
+ pci_config_set8(pci_conf, PCI_HEADER_TYPE, PCI_HEADER_TYPE_BRIDGE);
+
+ ich9_d2pbr_reset(d);
+ return b;
+}
+
+
+/* ICH9 LPC PCI to ISA bridge */
+struct ICH9_LPCDevice {
+ PCIDevice d;
+
+ int pci_irq_levels[ICH9_LPC_NB_PIRQS];
+
+ APMState apm;
+ struct ich9_lpc_pm_regs pm;
+};
+
+static struct ICH9_LPCDevice *ich9_pci_to_lpc(PCIDevice *d)
+{
+ return (struct ICH9_LPCDevice*)d;
+}
+
+static struct ICH9_LPCDevice *ich9_lpc;
+
+static void ich9_lpc_reset(struct ICH9_LPCDevice *lpc)
+{
+ uint8_t *pci_conf = lpc->d.config;
+ int i;
+
+ pci_config_set16(pci_conf, PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+
+ /* XXX capability isn't supported yet */
+ pci_config_set16(pci_conf, PCI_STATUS,
+ PCI_STATUS_DEVSEL_MEDIUM /* | PCI_STATUS_CAPABILITIES */);
+
+ for (i = 0; i < 4; i++) {
+ pci_config_set8(pci_conf, ICH9_LPC_PIRQA_ROUT + 1,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ for (i = 0; i < 4; i++) {
+ pci_config_set8(pci_conf, ICH9_LPC_PIRQE_ROUT + 1,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ pci_config_set32(pci_conf, ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
+ pci_config_set32(pci_conf, ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
+}
+
+static int ich9_lpc_pic_irq(struct ICH9_LPCDevice *lpc, int irq_num)
+{
+ switch (irq_num) {
+ case 0 ... 3:
+ return lpc->d.config[ICH9_LPC_PIRQA_ROUT + irq_num];
+ case 4 ... 7:
+ return lpc->d.config[ICH9_LPC_PIRQE_ROUT + (irq_num - 4)];
+ default:
+ break;
+ }
+ assert(0);
+ return 0;
+}
+
+static void ich9_lpc_set_irq(qemu_irq *pic, int irq_num, int level)
+{
+ int i, pic_irq, pic_level;
+
+ assert(0 <= irq_num && irq_num < 8);
+ ich9_lpc->pci_irq_levels[irq_num] = level;
+
+ /* XXX: check ICH9_LPC_PIRQ_ROUT_IRQEN bit */
+
+ /* now we change the pic irq level according to the piix irq mappings */
+ /* XXX: optimize */
+ pic_irq = ich9_lpc_pic_irq(ich9_lpc, irq_num);
+
+ /* XXX: IRQ 16 - 23 */
+ if (pic_irq < 16) {
+ /* The pic level is the logical OR of all the PCI irqs mapped
+ to it */
+ pic_level = 0;
+ for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
+ if (pic_irq == ich9_lpc_pic_irq(ich9_lpc, i)) {
+ pic_level |= ich9_lpc->pci_irq_levels[i];
+ }
+ }
+ qemu_set_irq(pic[pic_irq], pic_level);
+ }
+}
+
+/* APM */
+static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
+{
+#if 0
+ struct ICH9_LPCDevice *lpc = arg;
+
+ /* XXX: TODO */
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE 0x2
+#define ICH9_APM_ACPI_DISABLE 0x3
+
+ /* ACPI specs 3.0, 4.7.2.5 */
+ if (val == ACPI_ENABLE) {
+ lpc->pmcntrl |= ACPI_BITMASK_SCI_ENABLE;
+ } else if (val == ACPI_DISABLE) {
+ lpc->pmcntrl &= ~ACPI_BITMASK_SCI_ENABLE;
+ }
+#endif
+
+ /* XXX: TODO */
+ /* SMI_EN = PMBASE + 30
+ * SMI control and enable register
+ */
+#if 0
+ if ((SMI_EN register) & APMC_EN) {
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ }
+#endif
+}
+
+/* config:PMBASE */
+static void
+ich9_lpc_pmbase_update(PCIDevice *d, uint32_t addr, uint32_t data, int len)
+{
+ uint32_t pm_io_base = pci_config_get32(d->config, ICH9_LPC_PMBASE);
+ pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
+
+ ich9_pm_iospace_update(&ich9_pci_to_lpc(d)->pm, pm_io_base);
+}
+
+static void ich9_lpc_save(QEMUFile* f, void *opaque)
+{
+ struct ICH9_LPCDevice *lpc = opaque;
+ int i;
+
+ pci_device_save(&lpc->d, f);
+
+ for (i = 0; i < ICH9_LPC_NB_PIRQS; i++)
+ qemu_put_be32(f, lpc->pci_irq_levels[i]);
+
+ ich9_pm_save(f, &lpc->pm);
+}
+
+static int ich9_lpc_load(QEMUFile* f, void *opaque, int version_id)
+{
+ struct ICH9_LPCDevice *lpc = opaque;
+ int ret, i;
+
+ ret = pci_device_load(&lpc->d, f);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ICH9_LPC_NB_PIRQS; i++)
+ lpc->pci_irq_levels[i] = qemu_get_be32(f);
+
+ ich9_pm_load(f, &lpc->pm, version_id);
+ ich9_lpc_pmbase_update(&lpc->d,
+ 0, 0, 0 /* don't care those args */);
+ return 0;
+}
+
+static void ich9_set_sci(void *opaque, int irq_num, int level)
+{
+ /* opaque = pic */
+ assert(irq_num == 0);
+ ich9_lpc_set_irq(opaque, 1/* SCI = PIRQB# */, level);
+}
+
+static qemu_irq *ich9_lpc_allocate_sci_irq(qemu_irq *pic)
+{
+ return qemu_allocate_irqs(ich9_set_sci, pic, 1);
+}
+
+int ich9_lpc_init(PCIBus *bus, int devfn, qemu_irq *pic)
+{
+ struct ICH9_LPCDevice *lpc;
+ uint8_t *pci_conf;
+ qemu_irq *sci_irq;
+
+ assert(devfn == PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC));
+
+ lpc = (struct ICH9_LPCDevice*)pci_register_device(bus, ICH9_A2_LPC,
+ sizeof(*lpc), devfn,
+ NULL, NULL);
+ ich9_lpc = lpc;
+ pci_conf = lpc->d.config;
+
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ICH9_8); // ICH9 LPC
+ pci_config_set8(pci_conf, PCI_REVISION_ID, ICH9_A2_LPC_REVISION);
+ pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
+
+ // header_type = PCI_multifunction, generic
+ pci_config_set8(pci_conf, PCI_HEADER_TYPE,
+ PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION);
+
+ apm_init(&lpc->apm, ich9_apm_ctrl_changed, &lpc);
+
+ sci_irq = ich9_lpc_allocate_sci_irq(pic);
+ ich9_pm_init(&lpc->pm, sci_irq[0]);
+ pci_conf_initl(&lpc->d, ICH9_LPC_PMBASE, ich9_lpc_pmbase_update,
+ ICH9_LPC_PMBASE_DEFAULT);
+ pci_config_set32(lpc->d.config, ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
+
+ register_savevm(ICH9_A2_LPC, 0, ICH9_A2_LPC_SAVEVM_VERSION,
+ ich9_lpc_save, ich9_lpc_load, lpc);
+
+ ich9_lpc_reset(lpc);
+
+#if 0
+ /* XXX TODO */
+#define GPE_BASE_PIIX4 0xafe0
+#define ICH9_PMBASE_COMPAT ((GPE_BASE - ICH9_PMIO_GEP0_STS) |
ICH9_LPC_PMBASE_RTE)
+ pci_config_set32(pci_conf,ICH9_PMBASE_COMPAT);
+ qemu_acpi_gpe_init(pci_conf[ICH9_LPC_PMBASE] + ICH9_PMIO_GEP0_STS)
+#endif
+ return 0;
+}
diff --git a/hw/q35.h b/hw/q35.h
new file mode 100644
index 0000000..998bcd6
--- /dev/null
+++ b/hw/q35.h
@@ -0,0 +1,213 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "acpi_ich9.h"
+
+void gmch_init_memory_mappings(PCIDevice *d);
+PCIBus *gmch_init(PCIDevice **pgmch_state, qemu_irq *pic);
+
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int secondary_bus_num);
+int ich9_lpc_init(PCIBus *bus, int devfn, qemu_irq *pic);
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+
+void ich9_pm_init(struct ich9_lpc_pm_regs *pm, qemu_irq sci_irq);
+void ich9_pm_iospace_update(struct ich9_lpc_pm_regs *pm, uint32_t pm_io_base);
+void ich9_pm_save(QEMUFile* f, struct ich9_lpc_pm_regs *pm);
+void ich9_pm_load(QEMUFile* f, struct ich9_lpc_pm_regs *pm, int version_id);
+
+void ich9_hot_add_init(void);
+
+#define Q35_MASK(bit, ms_bit, ls_bit) ((((uint##bit##_t)1 <<
(ms_bit)) - 1) & ~(((uint##bit##_t)1 << ls_bit) - 1))
+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define Q35_HOST_BRIDGE "GMCH"
+
+#define Q35_HOST_BRIDGE_CONFIG_ADDR 0xcf8
+#define Q35_HOST_BRIDGE_CONFIG_DATA 0xcfc
+
+/* D0:F0 configuration space */
+#define Q35_HOST_BRIDGE_REVISION_DEFUALT 0x0
+
+#define Q35_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
+#define Q35_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
+#define Q35_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit
35:28 */
+#define Q35_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
+#define Q35_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
+#define Q35_HOST_BRIDGE_PCIEXBAR_LENGTH ((uint64_t)(0x2 << 1))
+#define Q35_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
+
+#define Q35_HOST_BRIDGE_PAM0 0x90
+#define Q35_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
+#define Q35_HOST_BRIDGE_PAM_AREA_SIZE 0x1000 /* 16KB */
+#define Q35_HOST_BRIDGE_PAM1 0x91
+#define Q35_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
+#define Q35_HOST_BRIDGE_PAM2 0x92
+#define Q35_HOST_BRIDGE_PAM3 0x93
+#define Q35_HOST_BRIDGE_PAM4 0x94
+#define Q35_HOST_BRIDGE_PAM5 0x95
+#define Q35_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
+#define Q35_HOST_BRIDGE_PAM6 0x96
+#define Q35_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
+#define Q35_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
+#define Q35_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
+#define Q35_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
+#define Q35_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
+#define Q35_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
+#define Q35_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
+#define Q35_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
+#define Q35_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
+
+
+#define Q35_HOST_BRDIGE_SMRAM 0x9d
+#define Q35_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
+#define Q35_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define Q35_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define Q35_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define Q35_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define Q35_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define Q35_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired
to b010 */
+#define Q35_HOST_BRIDGE_SMARM_C_BASE 0xa0000
+#define Q35_HOST_BRIDGE_SMRAM_C_END 0xc0000
+#define Q35_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
+#define Q35_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
+
+#define Q35_HOST_BRIDGE_ESMRAMC 0x9e
+#define Q35_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
+#define Q35_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
+#define Q35_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
+#define Q35_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
+#define Q35_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
+#define Q35_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
+#define Q35_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
+#define Q35_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
+#define Q35_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
+#define Q35_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
+
+
+/*
+ * ich9 part
+ */
+
+/* D30:F0 DMI-to-PCI brdige */
+#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
+#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
+
+#define ICH9_D2P_BRIDGE_DEV 30
+#define ICH9_D2P_BRIDGE_FUNC 0
+
+/* 1 pcie port on gmch and 6 pcie port on ich9,
+ the next bus # is 7 */
+#define ICH9_D2P_SECONDARY_DEFAULT 7
+
+#define ICH9_D2P_A2_REVISION 0x92
+
+
+/* D30:F1 LPC controller */
+#define ICH9_A2_LPC "ICH9 A2 LPC"
+#define ICH9_A2_LPC_SAVEVM_VERSION 0
+
+#define ICH9_LPC_DEV 30
+#define ICH9_LPC_FUNC 1
+
+#define ICH9_A2_LPC_REVISION 0x2
+#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
+
+#define ICH9_LPC_PMBASE 0x40
+#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
+#define ICH9_LPC_PMBASE_RTE 0x1
+#define ICH9_LPC_PMBASE_DEFAULT 0x1
+#define ICH9_LPC_ACPI_CTRL 0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
+#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
+#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
+
+#define ICH9_LPC_PIRQA_ROUT 0x60
+#define ICH9_LPC_PIRQB_ROUT 0x61
+#define ICH9_LPC_PIRQC_ROUT 0x62
+#define ICH9_LPC_PIRQD_ROUT 0x63
+
+#define ICH9_LPC_PIRQE_ROUT 0x68
+#define ICH9_LPC_PIRQF_ROUT 0x69
+#define ICH9_LPC_PIRQG_ROUT 0x6a
+#define ICH9_LPC_PIRQH_ROUT 0x6b
+
+#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
+#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
+#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x1
+
+#define ICH9_LPC_RCBA 0xf0
+#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
+#define ICH9_LPC_RCBA_EN 0x1
+#define ICH9_LPC_RCBA_DEFAULT 0x0
+
+/* D30:F1 power management I/O registers
+ offset from the address ICH9_LPC_PMBASE */
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_SIZE 128
+#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
+
+#define ICH9_PMIO_PM1_STS 0x00
+#define ICH9_PMIO_PM1_EN 0x02
+#define ICH9_PMIO_PM1_CNT 0x04
+#define ICH9_PMIO_PM1_TMR 0x08
+#define ICH9_PMIO_GPE0_STS 0x20
+#define ICH9_PMIO_GPE0_EN 0x28
+#define ICH9_PMIO_SMI_EN 0x30
+#define ICH9_PMIO_SMI_STS 0x34
+
+
+/* D30:F3 SMBus controller */
+#define ICH9_A2_SMB_REVISION 0x02
+#define ICH9_SMB_PI 0x00
+
+#define ICH9_SMB_SMBMBAR0 0x10
+#define ICH9_SMB_SMBMBAR1 0x14
+#define ICH9_SMB_SMBM_BAR 0
+#define ICH9_SMB_SMBM_SIZE (1 << 8)
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_SMB_BASE_BAR 4
+#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
+#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
+#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
+#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
+
+/* D30:F3 SMBus I/O and memory mapped I/O registers */
+#define ICH9_SMB_HST_STS 0x00
+#define ICH9_SMB_HST_CNT 0x02
+#define ICH9_SMB_HST_CMD 0x03
+#define ICH9_SMB_XMIT_SLVA 0x04
+#define ICH9_SMB_HST_D0 0x05
+#define ICH9_SMB_HST_D1 0x06
+#define ICH9_SMB_HOST_BLOCK_DB 0x07
+
+
+#endif /* HW_Q35_H */
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
new file mode 100644
index 0000000..41804d0
--- /dev/null
+++ b/hw/q35_smbus.c
@@ -0,0 +1,177 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pc_smbus.h"
+#include "pci.h"
+//#include "qemu-timer.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
+#include "kvm.h"
+
+#include "q35.h"
+
+typedef struct ICH9_SMBState {
+ PCIDevice dev;
+
+ PCSMBus smb;
+} ICH9_SMBState;
+
+#define ICH9_SMB_SAVEVM_VERSION_CURRENT 0
+
+#if 0
+#define SMBHSTSTS ICH9_SMB_HST_STS
+#define SMBHSTCNT ICH9_SMB_HST_CNT
+#define SMBHSTCMD ICH9_SMB_HST_CMD
+#define SMBHSTADD ICH9_SMB_XMIT_SLVA
+#define SMBHSTDAT0 ICH9_SMB_HST_D0
+#define SMBHSTDAT1 ICH9_SMB_HST_D1
+#define SMBBLKDAT ICH9_SMB_HOST_BLOCK_DB
+#endif
+
+static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
+{
+ return (ICH9_SMBState*)pci_dev;
+}
+
+
+static void ich9_smb_save(QEMUFile* f,void *opaque)
+{
+ ICH9_SMBState *s = opaque;
+
+ pci_device_save(&s->dev, f);
+}
+
+static int ich9_smb_load(QEMUFile* f,void* opaque,int version_id)
+{
+ ICH9_SMBState *s = opaque;
+ int ret;
+
+ if (version_id > ICH9_SMB_SAVEVM_VERSION_CURRENT)
+ return -EINVAL;
+
+ ret = pci_device_load(&s->dev, f);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static void ich9_smb_reset(void *opaque)
+{
+ //ICH9_SMBState *s = opaque;
+ //uint8_t *pci_conf = s->dev.config;
+
+ /* XXX not yet */
+}
+
+static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if (hostc & ICH9_SMB_HOSTC_HST_EN && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint32_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ smb_ioport_writeb(&s->smb, offset, val);
+ }
+}
+
+static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if (hostc & ICH9_SMB_HOSTC_HST_EN && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint32_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ return smb_ioport_readb(&s->smb, offset);
+ }
+
+ return 0xff;
+}
+
+static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
+ uint32_t addr, uint32_t size, int type)
+{
+ ICH9_SMBState *s = ich9_pci_to_smb(dev);
+
+ assert(size == ICH9_SMB_SMB_BASE_SIZE);
+ assert(type == PCI_ADDRESS_SPACE_IO);
+
+ register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
+ register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
+}
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
+{
+ ICH9_SMBState *s;
+ uint8_t *pci_conf;
+
+ s = (ICH9_SMBState *)pci_register_device(bus,
+ "ICH9 SMB", sizeof(ICH9_SMBState),
+ devfn, NULL, NULL);
+ pci_conf = s->dev.config;
+ pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ICH9_6);
+
+ pci_config_set16(pci_conf, PCI_STATUS,
+ PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
+ pci_conf_initw(&s->dev, PCI_STATUS, NULL,
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+
+ pci_config_set8(pci_conf, PCI_REVISION_ID, ICH9_A2_SMB_REVISION);
+ pci_config_set8(pci_conf, PCI_CLASS_INTERFACE, ICH9_SMB_PI);
+
+ pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_SMBUS);
+ pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
+
+ /* XXX: D31IP.SMIP in chipset configuration space */
+ pci_config_set8(pci_conf, PCI_INTERRUPT_PIN, 0x01); // interrupt pin 1
+
+ pci_config_set8(pci_conf, ICH9_SMB_HOSTC, 0);
+
+
+ /* XXX:
+ * paralell_hds[0]
+ * serial_hds[0]
+ * serial_hds[0]
+ * fdc
+ */
+
+ // XXX smb_io_base
+ pci_config_set8(pci_conf, ICH9_SMB_HOSTC, 0);
+ /* XXX bar0, bar1: 64bit BAR support*/
+ pci_register_bar(&s->dev, ICH9_SMB_SMB_BASE_BAR,
+ ICH9_SMB_SMB_BASE_SIZE, PCI_ADDRESS_SPACE_IO,
+ &ich9_smb_map_ioport);
+
+ register_savevm("ich9_smb", 0, ICH9_SMB_SAVEVM_VERSION_CURRENT,
+ ich9_smb_save, ich9_smb_load, s);
+
+ pc_smbus_init(&s->smb);
+ qemu_register_reset(ich9_smb_reset, 0, s);
+
+ return s->smb.smbus;
+}
--
yamahata
- [Qemu-devel] [PATCH 11/18] pc.c: introduce a function to allocate cpu irq., (continued)
- [Qemu-devel] [PATCH 11/18] pc.c: introduce a function to allocate cpu irq., Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 14/18] pc.c: split out memory allocation from pc_init1() into pc_memory_init(), Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 06/18] acpi.c: split acpi.c into the common part and the piix4 part., Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 10/18] pc.c: remove a global variable, RTCState *rtc_state., Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 18/18] pc.c: split out piix specific part from pc.c into pc_piix.c, Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 17/18] pc.c: split out pci device init from pc_init1() into pc_pci_device_init(), Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 15/18] pc.c: split out vga initialization from pc_init1() into pc_vga_init()., Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 12/18] pc.c: make pc_init1() not refer ferr_irq directly., Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH 16/18] pc.c: split out basic device init from pc_init1() into pc_basic_device_init(), Isaku Yamahata, 2009/06/18
- [Qemu-devel] [PATCH] q35 chipset based pc. wip.,
Isaku Yamahata <=